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UPD178004A Datasheet(PDF) 35 Page - NEC |
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UPD178004A Datasheet(HTML) 35 Page - NEC |
35 / 56 page 35 µPD178004A, 178006A, 178016A, 178018A (2) SERIAL INTERFACE (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... internal clock output) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK0 cycle time tKCY1 4.5 V ≤ VDD ≤ 5.5 V 800 ns 3.5 V ≤ VDD < 4.5 V 1 600 ns SCK0 high-/low-level width tKH1, 4.5 V ≤ VDD ≤ 5.5 V tKCY1/2 – 50 ns tKL1 3.5 V ≤ VDD < 4.5 V tKCY1/2 – 100 ns SI0 setup time (to SCK0 ↑)tSIK1 4.5 V ≤ VDD ≤ 5.5 V 100 ns 3.5 V ≤ VDD < 4.5 V 150 ns SI0 hold time (from SCK0 ↑)tKSI1 400 ns SO0 output delay time from SCK0 ↓ tKSO1 C = 100 pF Note 300 ns Note C is the load capacitance of SO0 output line. (ii) 3-wire serial I/O mode (SCK0 ... external clock input) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK0 cycle time tKCY2 4.5 V ≤ VDD ≤ 5.5 V 800 ns 3.5 V ≤ VDD < 4.5 V 1 600 ns SCK0 high-/low-level width tKH2, 4.5 V ≤ VDD ≤ 5.5 V 400 ns tKL2 3.5 V ≤ VDD < 4.5 V 800 ns SI0 setup time (to SCK0 ↑)tSIK2 100 ns SI0 hold time (from SCK0 ↑)tKSI2 400 ns SO0 output delay time from SCK0 ↓ tKSO2 C = 100 pF Note 300 ns SCK0 at rising or falling edge time tR2, tF2 1 000 ns Note C is the load capacitance of SO0 output line. |
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