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UPD178002 Datasheet(PDF) 15 Page - NEC |
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UPD178002 Datasheet(HTML) 15 Page - NEC |
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15 / 48 page  15 µPD178002, 178003 Data Sheet U12628EJ3V0DS00 5.2 Clock Generator The instruction execution time can be changed as follows. 0.44 µs/0.88 µs/1.78 µs/3.56 µs/7.11 µs/14.22 µs (4.5 MHz crystal resonator for system clock.) Figure 5-1. Clock Generator Block Diagram 5.3 Timer Three timer channels are incorporated. • Basic timer: 1 channel • 8-bit timer/event counter: 2 channels Figure 5-2. Basic Timer Block Diagram Frequency divider 4.5 MHz INTTMC X1 X2 fXX Prescaler System clock oscillator Clock to peripheral hardware other than the above. Clock to the PLL frequency synthesizer, basic timer, and buzzer output control circuit. CPU clock (fCPU) Standby control circuit Wait control circuit To INTP0 sampling clock 2 fXX 22 fXX 23 fXX 24 fXX Prescaler Selector Selector fX fX 2 STOP Frequency divider |
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Similar Description - UPD178002 |
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