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UPD178002 Datasheet(PDF) 9 Page - NEC |
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UPD178002 Datasheet(HTML) 9 Page - NEC |
9 / 48 page 9 µPD178002, 178003 Data Sheet U12628EJ3V0DS00 3.2 Non-port Pins Pin Name I/O Function After Alternate Reset Function INTP0, Input External maskable interrupt input for which the valid edge (rising edge, Input P00, P01 INTP1 falling edge, or both rising and falling edges) can be specified. SI1 Input Serial interface serial data input Input P20 SO1 Output Serial interface serial data output Input P21 SCK1 I/O Serial interface serial clock input/output Input P22 TI1 Input External count clock input to 8-bit timer (TM1) Input P33 TI2 External count clock input to 8-bit timer (TM2) P34 BEEP Output Buzzer output Input P36 ANI0 to Input A/D converter analog input Input P10 to P15 ANI5 EO0, EO1 Output Error out output from charge pump of the PLL frequency synthesizer — — VCOL Input Inputs PLL local band frequency (In HF, MF mode) — — VCOH Input Inputs PLL local band frequency (In VHF mode) — — AMIFC Input Inputs AM intermediate frequency counter — — FMIFC Input Inputs FM intermediate frequency or AM intermediate frequency counter — — RESET Input System reset input — — X1 Input Connecting crystal resonator for system clock oscillation — — X2 — —— REGOSC — Oscillation regulator. Connect to GND via a 0.1 µF capacitor. — — REGCPU — CPU power supply regulator. Connect to GND via a 0.1 µF capacitor. — — VDD — Positive power supply — — GND — Ground —— VDDPORT — Positive power supply for port block — — GNDPORT — Ground for port block — — VDDPLLNote — Positive power supply for PLL — — GNDPLLNote — Ground for PLL — — IC — Internally connected. Connect directly to GND or GNDPORT. — — Note Connect a capacitor of about 1000pF between the VDDPLL pin and GNDPLL pin. |
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