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UPD178002 Datasheet(PDF) 7 Page - NEC |
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UPD178002 Datasheet(HTML) 7 Page - NEC |
7 / 48 page ![]() 7 µPD178002, 178003 Data Sheet U12628EJ3V0DS00 2. BLOCK DIAGRAM Remark The internal ROM capacity varies depending on the product. 8-bit timer/ event counter 1 8-bit timer/ event counter 2 Basic timer Serial interface 1 A/D Converter Interrupt control Buzzer output System control RAM 78K/0 CPU core ROM 6 6 8 8 8 8 8 6 3 3 P00 P01 to P06 Frequency counter PLL voltage regulator PLL Voltage regulator TI1/P33 TI2/P34 SI1/P20 SO1/P21 SCK1/P22 RESET X1 X2 VDDPORT GNDPORT VDD RESET CPU Peripheral REGOSC REGCPU GND VOSC VCPU ANI0/P10 to ANI2/P12 BEEP/P36 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 12 Port 13 P10 to P15 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P120 to P125 P132 to P134 AMIFC FMIFC EO0 EO1 VCOL VCOH VDDPLL GNDPLL IC INTP0/P00 INTP1/P01 |
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Similar Description - UPD178002 |
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