UPD178002 datasheet(3/48 Pages) NEC

Part #	UPD178002

Description	8-BIT SINGLE-CHIP MICROCONTROLLERS

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Manufacturer	NEC [NEC]

Direct Link	http://www.nec.com/

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µPD178002, 178003

3

Data Sheet U12628EJ3V0DS00

OVERVIEW OF FUNCTIONS

Part Number

µPD178002

µPD178003

Item

Internal

ROM (ROM configuration)

16 Kbytes (mask ROM)

24 Kbytes (mask ROM)

memory

High-speed RAM

512 bytes

General-purpose registers

8 bits

× 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time

0.44

µs/0.88 µs/1.78 µs/3.56 µs/7.11 µs/14.22 µs (with 4.5 MHz crystal

resonator used)

Instruction set

• 16-bit operation

• Multiply/divide (8 bits

× 8 bits, 16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjust, etc.

I/O port

Total:

62

CMOS input:

1

CMOS I/O:

54

N-ch open-drain I/O:

4

N-ch open-drain output:

3

A/D converter

8-bit resolution

× 3 channels

Serial interface

• 3-wire serial I/O mode: 1 channel

Timer

• Basic timer (timer carry FF (10 Hz)):

1 channel

• 8-bit timer/event counter:

2 channels

Buzzer (BEEP) output

1.5 kHz, 3 kHz, 6 kHz

Vectored

Maskable

Internal: 5, external: 2

interrupt

Software

1

sources

Test input

Internal: 1

PLL frequency

Division mode

Two types

synthesizer

• Direct division mode (VCOL pin)

• Pulse swallow mode (VCOH and VCOL pins)

Reference frequency

7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz)

Charge pump

Error out output: 2

Phase comparator

Unlock detectable by program

Frequency counter

• Frequency measurement

• AMIFC pin: for 450 kHz count

• FMIFC pin: for 450 kHz/10.7 MHz count

Standby function

• HALT mode

• STOP mode

Reset

• Reset by RESET pin

• Reset by power-on clear circuit (3-value detection)

• Detection of less than 4.5 VNote (CPU clock: fX)

• Detection of less than 3.5 VNote (CPU clock: fX/2 or less and on power

application)

• Detection of less than 2.5 VNote (in STOP mode)

Supply voltage

• VDD = 4.5 to 5.5 V (with PLL operating)

• VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less)

• VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX)

Package

• 80-pin plastic QFP (14

× 14 mm, 0.65 mm pitch)

One-time PROM

µPD178P018A

Note

These voltage values are maximum values. The reset is actually executed at a voltage lower than these

values.

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