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2SJ555 Datasheet(PDF) 7 Page - Renesas Technology Corp

Part # 2SJ555
Description  Silicon P Channel MOS FET
Download  10 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

2SJ555 Datasheet(HTML) 7 Page - Renesas Technology Corp

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2SJ555
Rev.3.00 Sep 07, 2005 page 5 of 7
Source to Drain Voltage
VSD (V)
Reverse Drain Current vs.
Source to Drain Voltage
500
25
50
75
100
125
150
0
100
200
300
400
Channel Temperature Tch (°C)
Maximum Avalanche Energy vs.
Channel Temperature Derating
IAP = –60 A
VDD = –25 V
duty < 0.1 %
Rg
≥ 50 Ω
–100
0
–20
–40
–60
–80
0
–0.4
–0.8
–1.2
–1.6
–2.0
Pulse Test
–5 V
VGS = 0
–10 V
Avalanche Test Circuit
Avalanche Waveform
0
ID
VDS
IAP
V(BR)DSS
VDD
EAR =
• L • IAP
2 •
2
1
VDSS
VDSS – VDD
D.U.T
Rg
IAP
Monitor
VDS
Monitor
VDD
50
Ω
Vin
–15 V
L
Pulse Width PW (S)
Normalized Transient Thermal Impedance vs. Pulse Width
3
1
0.3
0.1
0.03
0.01
10
µ
100
µ
1 m
10 m
100 m
1
10
Tc = 25°C
D = 1
0.5
0.2
0.1
0.05
0.02
0.01
1shot
pul
se
PDM
PW
T
D =
PW
T
θch – c (t) = γ s (t) • θch – c
θch – c = 1.0°C/W, Tc = 25°C


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