CDCL1810A

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SLLSEL1 – NOVEMBER 2014

9.3 Feature Description

9.3.1 Output Enable/Disable

The CDCL1810A does not have an output synchronization feature like the CDCL1810. The CDCL1810A ensures

that all outputs stay enabled during any device communication like output enable/disable. Divider changes will

apply immediately at the outputs. This may cause a glitch and may result in different phase offsets between both

dividers.

Figure 5. Device Status Flow Chart

9.3.2 SDA/SCL Interface

This section describes the SDA/SCL interface of the CDCL1810A device. The CDCL1810A operates as a slave

device of the industry standard 2-pin SDA/SCL bus. It operates in the fast-mode at a bit-rate of up to 400 kbit/s

and supports 7-bit addressing compatible with the popular 2-pin serial interface standard.

9.3.2.1 SDA/SCL Bus Slave Device Address

A6

A5

A4

A3

A2

A1

A0

R/W

1

1

0

1

0

ADD1

ADD0

0/1

The device address is made up of the fixed internal address, 11010 (A6:A2), and configurable external pins

ADD1 (A1) and ADD0 (A0). Four different devices with addresses 1101000, 1101001, 1101010 and 1101011,

can be addressed via the same SDA/SCL bus interface. The least significant bit of the address byte designates a

write or read operation.

R/W Bit:

0 = write to CDCL1810A device

1 = read from CDCL1810A device

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