V

DD

CLKN

CLKP

YN[4:0]

YP[4:0]

YN[9:5]

YP[9:5]

SDA/SCL

See Note 1

Divider Setting

CML

CML

SDA/SCL

V

SS

LVDS

CML

CML

Divider

P0

Divider

P1

Control

SDA/SCL

Differential

LVDSInput

Upto650MHz

5Differential

CMLOutputs

Upto650MHz

5Differential

CMLOutputs

Upto650MHz

DIVIDER

DIVIDER

CDCL1810A

SLLSEL1 – NOVEMBER 2014

www.ti.com

9 Detailed Description

9.1 Overview

The CDCL1810A is a high performance fanout clock buffer that features two banks of independent integer

dividers ranging from 1 to 80. CDCL1810A is designed in a way that individual outputs can be configured -- or

reconfigured -- without impacting operation of other outputs.

9.2 Functional Block Diagram

Figure 3. CDCL1810A Simplified Schematic

Note 1: Outputs can be disabled to floating. When outputs are left floating, internal 50

YN and YP to VDD.

Figure 4. Functional Block Diagram

10

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