CDCL1810ARGZT datasheet(7/30 Pages) TI1

Part #	CDCL1810ARGZT

Description	Single 1.8 V Supply

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CDCL1810A

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SLLSEL1 – NOVEMBER 2014

8.5 DC Electrical Characteristics

Over recommended operating conditions (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All outputs enabled; VDD = VDD,typ

IVDD

Total current from digital 1.8V supply

212

mA

650MHz LVDS input

All outputs enabled; AVDD = VDD,typ

IAVDD

Total current from analog 1.8V supply

16

mA

650MHz LVDS input

VIL,CMOS

Low level CMOS input voltage

VDD = 1.8V

–0.2

0.6

V

VIH,CMOS

High level CMOS input voltage

VDD = 1.8V

VDD –0.6

VDD

V

IIL,CMOS

Low level CMOS input current

VDD = VDD,max, VIL = 0.0V

–120

μA

IIH,CMOS

High level CMOS input current

VDD = VDD,max, VIH = 1.9V

65

μA

Low level CMOS output voltage for the

VOL,SDA

Sink current = 3 mA

0

0.2VDD

V

SDA pin

IOL,CMOS

Low level CMOS output current

8

mA

8.6

AC Electrical Characteristics

Over recommended operating conditions (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential input impedance for the LVDS

ZD,IN

90

132

Ω

input terminals

VCM,IN

Common-mode voltage, LVDS input

1125

1200

1375

mV

VS,IN

Single-ended LVDS input voltage swing

100

600

mVPP

VD,IN

Differential LVDS input voltage swing

200

1200

tR,OUT,

Output signal rise/fall time

20%–80%

100

ps

tF,OUT

VCM,OUT

Common-mode voltage, CML outputs

VDD – 0.31

VDD – 0.23

VDD – 0.19

V

VS,OUT

Single-ended CML output voltage swing

ac-coupled

180

230

280

measured in a 50-

Ω scope;

mVPP

VD,OUT

Differential CML output voltage swing

The CML output incorporates

360

460

560

50-

Ω resistors to VDD

FIN

Clock input frequency

650

MHz

FOUT

Clock output frequency

650

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