Y0

Y1

Enable

Y[4:0], div by 2

Y[9:5], div by 6

CDCL1810A

www.ti.com

SLLSEL1 – NOVEMBER 2014

Application Information (continued)

10.1.1.3 Application Curves

Figure 10. Output Group Divider Change

Figure 11. Individual Output Disable/Enable

11 Power Supply Recommendations

The device is designed to operate from an input voltage supply of 1.8 V for analog supply (AVDD) and core

supply (VDD). Both AVDD and VDD can be supplied by a single source.

12 Layout

12.1 Layout Guidelines

•

Keep the connections between the bypass capacitors and the power supply on the device as short as

possible.

•

Ground the other side of the capacitor using a low impedance connection to the ground plane.

•

If the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to

the Thermal Dissipation Pad can be difficult.

•

For component side mounting, use 0201 body size capacitors to facilitate signal routing.

NOTE

device performance will be severely impacted if the exposed thermal pad is not grounded

appropriately.

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