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CDCL1810ARGZR Datasheet(PDF) 17 Page - Texas Instruments |
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CDCL1810ARGZR Datasheet(HTML) 17 Page - Texas Instruments |
17 / 30 page ![]() CDCL1810A www.ti.com SLLSEL1 – NOVEMBER 2014 9.6.1.7 Byte 6: POWER UP REFERENCE BIT BIT NAME DESCRIPTION/FUNCTION TYPE CONDITION TO 7 ENDRV3 YP[3], YN[3] enable; if 0 output is disabled R/W 1 6 ENDRV2 YP[2], YN[2] enable; if 0 output is disabled R/W 1 5 ENDRV1 YP[1], YN[1] enable; if 0 output is disabled R/W 1 4 ENDRV0 YP[0], YN[0] enable; if 0 output is disabled R/W 1 3 RES Reserved R/W 0 2 RES Reserved R/W 0 1 RES Reserved R/W 0 0 RES Reserved R/W 0 Table 11. Divide Ratio Settings for Post-Divider P0 or P1 DIVIDE SELP1[3] or SELP1[2] or SELP1[1] or SELP1[0] or RATIO SELP0[3] SELP0[2] SELP0[1] SELP0[0] NOTES 1 0 0 0 0 Default 2 0 0 0 1 4 0 0 1 0 5 0 0 1 1 8 0 1 0 0 10 0 1 0 1 16 0 1 1 0 20 0 1 1 1 32 1 0 0 0 40 1 0 0 1 80 1 0 1 0 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: CDCL1810A |
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