8

Fault Protection

The HIP6304 protects the microprocessor and the entire

power system from damaging stress levels. Within the

HIP6304 both Over-Voltage and Over-Current circuits are

incorporated to protect the load and regulator.

Over-Voltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE over-voltage condition is detected when

the VSEN pin goes more than 15% above the programmed

VID level.

The over-voltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

POR and Soft-Start sequence.

During a latched over-voltage, the PWM outputs will be

driven either low or three state, depending upon the VSEN

input. PWM outputs are driven low when the VSEN pin

detects that the CORE voltage is 15% above the

programmed VID level. This condition drives the PWM

outputs low, resulting in the lower or synchronous rectifier

MOSFETs to conduct and shunt the CORE voltage to

ground to protect the load.

If after this event, the CORE voltage falls below the over-

voltage limit (plus some hysteresis), the PWM outputs will

three state. The HIP6601 family drivers pass the three state

information along, and shuts off both upper and lower

MOSFETs. This prevents “dumping” of the output capacitors

back through the lower MOSFETs, avoiding a possibly

destructive ringing of the capacitors and output inductors. If

the conditions that caused the over-voltage still persist, the

clamped to ground, as a hysteretic shunt regulator.

Under-Voltage

The VSEN pin also detects when the CORE voltage falls

more than 10% below the VID programmed level. This

causes PGOOD to go low, but has no other effect on

operation and is not latched. There is also hysteresis in this

detection point.

Over-Current

In the event of an over-current condition, the over-current

protection circuit reduces the average current delivered to

less than 25% of the current limit. When an over-current

condition is detected, the controller forces all PWM outputs

into a three state mode. This condition results in the gate

driver removing drive to the output stages. The HIP6304

goes into a wait delay timing cycle that is equal to the Soft-

Start ramp time. PGOOD also goes “low” during this time

due to VSEN going below its threshold voltage. To lower the

average output dissipation, the Soft-Start initial wait time is

increased from 32 to 2048 cycles, then the Soft-Start ramp is

initiated. At a PWM frequency of 200kHz, for instance, an

over-current detection would cause a dead time of 10.24ms,

then a ramp of 10.08ms.

At the end of the delay, PWM outputs are restarted and the

Soft-Start ramp is initiated. If a short is present at that time,

the cycle is repeated. This is the hiccup mode.

Figure 6 shows the supply shorted under operation and the

hiccup operating mode described above. Note that due to

the high short circuit current, over-current is detected before

completion of the start-up sequence so the delay is not quite

as long as the normal Soft-Start cycle.

CORE Voltage Programming

The voltage identification pins (VID0, VID1, VID2, and VID3)

by an internal 20

µA current source and accepts

open-collector/open-drain/open-switch-to-ground or

standard low-voltage TTL or CMOS signals.

Table 1 shows the nominal DAC voltage as a function of the

VID codes. The power supply system is

±1% accurate over

the operating temperature and voltage range.

TABLE 1. VOLTAGE IDENTIFICATION CODES

VID3

VID2

VID1

VID0

VDAC

1111

1.30

1110

1.35

1101

1.40

1100

1.45

1011

1.50

1010

1.55

1001

1.60

1000

1.65

0111

1.70

0110

1.75

0101

1.80

0100

1.85

0011

1.90

0010

1.95

0001

2.00

0000

2.05

PGOOD

SHORT

50A/DIV

CURRENT

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY

CORE LOAD CURRENT = 31A, 5V LOAD = 5A

SHORT APPLIED HERE

FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP

HIP6304