7

condition by slowly charging the discharged output

capacitors. This voltage rise is initiated by an internal DAC

that slowly raises the reference voltage to the error amplifier

input. The voltage rise is controlled by the oscillator

frequency and the DAC within the HIP6304, therefore, the

output voltage is effectively regulated as it rises to the final

programmed CORE voltage value.

For the first 32 PWM switching cycles, the DAC output

remains inhibited and the PWM outputs remain three stated.

From the 33rd cycle and for another, approximately 150

cycles the PWM output remains low, clamping the lower

output MOSFETs to ground, see Figure 3. The time

variability is due to the Error Amplifier, Sawtooth Generator

and Comparators moving into their active regions. After this

short interval, the PWM outputs are enabled and increment

the PWM pulse width from zero duty cycle to operational

pulse width, thus allowing the output voltage to slowly reach

the CORE voltage. The CORE voltage will reach its

programmed value before the 2048 cycles, but the PGOOD

output will not be initiated until the 2048th PWM switching

cycle.

160

µs, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

described above, the PWM outputs are initiated and the

voltage rises in 10.08ms, for a total delay time DT of

10.24ms.

Figure 3 shows the start-up sequence as initiated by a fast

short rise to the three state level in PWM 1 output during first

32 PWM cycles.

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the Soft-Start duration is a

function of the Channel Frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram on page 2).

Figure 5 shows the regulator operating from an ATX supply.

In this figure, note the slight rise in PGOOD as the 5V supply

rises. The PGOOD output stage is made up of NMOS and

becomes active slightly before the NMOS transistor pulls

“down”, generating the slight rise in the PGOOD voltage.

Note that Figure 5 shows the 12V gate driver voltage

available before the 5V supply to the HIP6304 has reached

its threshold level. If conditions were reversed and the 5V

supply was to rise first, the start-up sequence would be

different. In this case the HIP6303 will sense an over-current

condition due to charging the output capacitors. The supply

will then restart and go through the normal Soft-Start cycle.

.

PWM 1

PGOOD

5V

OUTPUT

DELAY TIME

FIGURE 3. START-UP OF A SYSTEM OPERATING AT 500kHz

PGOOD

5V

V COMP

DELAY TIME

FIGURE 4. START-UP A SYSTEM OPERATING AT 200kHz

12V ATX

SUPPLY

PGOOD

5 V ATX

SUPPLY

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

FREQUENCY 200kHz

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

HIP6304