AD9460_15 datasheet(23/32 Pages) AD

Part #	AD9460

Description	16-Bit, 80 MSPS/105 MSPS ADC

Download	32 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

Logo

23 / 32 page

AD9460

Rev. 0 | Page 23 of 32

DIGITAL OUTPUTS

LVDS Mode

The off-chip drivers on the chip can be configured to provide

LVDS-compatible output levels via Pin 3 (OUTPUT MODE).

LVDS outputs are available when OUTPUT MODE is CMOS

logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET

resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic

performance, including both SFDR and SNR, maximizes when

using the AD9460 in LVDS mode; designers are encouraged to

take advantage of this mode. The AD9460 outputs include com-

plementary LVDS outputs for each data bit (Dx+/Dx−), the

overrange output (OR+/OR−), and the output data clock output

(DCO+/DCO−). The RSET resistor current is multiplied on-chip,

setting the output current at each output equal to a nominal

3.5 mA (11 × IRSET). A 100 Ω differential termination resistor

placed at the LVDS receiver inputs results in a nominal 350 mV

swing at the receiver. LVDS mode facilitates interfacing with

LVDS receivers in custom ASICs and FPGAs that have LVDS

capability for superior switching performance in noisy environ-

ments. Single point-to-point net topologies are recommended,

with a 100 Ω termination resistor located as close to the receiver

as possible. It is recommended to keep the trace length less than

two inches and to keep differential output trace lengths as equal

as possible.

CMOS Mode

In applications that can tolerate a slight degradation in dynamic

performance, the AD9460 output drivers can be configured to

interface with 2.5 V or 3.3 V logic families by matching

DRVDD to the digital supply of the interfaced logic. CMOS

outputs are available when OUTPUT MODE is CMOS logic

low (or AGND for convenience). In this mode, the output data

bits, Dx, are single-ended CMOS, as is the overrange output,

OR+. The output clock serves as a differential CMOS signal,

DCO+/DCO−. Lower supply voltages are recommended to

avoid coupling switching transients back to the sensitive analog

sections of the ADC. Minimize the capacitive load to the CMOS

outputs and connect each output to a single gate through a

series resistor (220 Ω) to minimize switching transients caused

by the capacitive loading.

TIMING

The AD9460 provides latched data outputs with a pipeline delay

of 13 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and

Figure 3 for detailed timing diagrams.

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9460 determines

the coding format of the output data. This pin is 3.3 V CMOS

compatible, with logic high (or AVDD1, 3.3 V) selecting twos

complement and DFS logic low (AGND) selecting offset binary

format. Table 10 summarizes the output coding.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility,

as well as the pinout of the digital outputs. This pin is a CMOS-

compatible input. With OUTPUT MODE = 0 (AGND), the

AD9460 outputs are CMOS compatible, and the pin assignment

for the device is as defined in Table 8. With OUTPUT MODE = 1

(AVDD1, 3.3 V), the AD9460 outputs are LVDS compatible, and

the pin assignment for the device is as defined in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS

logic low (AGND) on DCS MODE enables the DCS, and logic

high (AVDD1, 3.3 V) disables the controller.

SFDR Enhancement

Under certain conditions, the SFDR performance of the AD9460

improves by adding some additional power to the core of the

ADC. The SFDR control pin (Pin 100) is a CMOS-compatible

control pin to optimize the configuration of the AD9460 analog

front end. Connecting SFDR to AGND optimizes SFDR

performance for applications with analog input frequencies

<200 MHz for 80 MSPS and 105 MSPS speed grades. For

applications with analog inputs >200 MHz, this pin should be

connected to AVDD1 for optimum SFDR performance; power

dissipation from AVDD2 increases by ~70 mW for the

AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

Table 10. Digital Output Coding

Code

VIN+ − VIN−

Input Span = 3.4 V p-p (V)

VIN+ − VIN−

Input Span = 2 V p-p (V)

Digital Output

Offset Binary (D15…D0)

Digital Output

Twos Complement (D15…D0)

65,536

+1.700

+1.000

1111 1111 1111 1111

0111 1111 1111 1111

32,768

0

1000 0000 0000 0000

0000 0000 0000 0000

32,767

−0.000052

−0.000031

0111 1111 1111 1111

1111 1111 1111 1111

0

−1.70

−1.00

0000 0000 0000 0000

1000 0000 0000 0000

Similar Part No. - AD9460_15

Manufacturer	Part #	Datasheet	Description
Analog Devices	AD9460-105EB-BB	902Kb / 28P	High Speed ADC USB FIFO Evaluation Kit REV. 0
	AD9460-105EB-IF	902Kb / 28P	High Speed ADC USB FIFO Evaluation Kit REV. 0
	AD9460-105LVDS/PCB	1Mb / 32P	16-Bit, 80 MSPS/105 MSPS ADC REV. 0
	AD9460-105LVDS/PCB	1Mb / 33P	16-Bit, 80 MSPS/105 MSPS ADC
	AD9460	1Mb / 33P	16-Bit, 80 MSPS/105 MSPS ADC

More results

Similar Description - AD9460_15

Manufacturer	Part #	Datasheet	Description
Analog Devices	AD9460	1Mb / 33P	16-Bit, 80 MSPS/105 MSPS ADC
	AD9460	1Mb / 32P	16-Bit, 80 MSPS/105 MSPS ADC REV. 0
	AD9432BSQZ-80	517Kb / 16P	12-Bit, 80 MSPS/105 MSPS ADC Rev. E
	AD9432	517Kb / 16P	12-Bit, 80 MSPS/105 MSPS ADC Rev. F
	AD9432	517Kb / 16P	12-Bit, 80 MSPS/105 MSPS ADC Rev. F
	AD9432	441Kb / 17P	12-Bit, 80 MSPS/105 MSPS ADC
Integrated Device Techn...	ADC1613D	656Kb / 41P	Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface
NXP Semiconductors	ADC1613D	389Kb / 43P	Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 02-23 April 2010
NXP Semiconductors	ADC1613D	622Kb / 43P	Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 3-9 February 2011
Integrated Device Techn...	ADC1613S	705Kb / 37P	Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface

More results

AD9460 Datasheet(PDF) 23 Page - Analog Devices

AD9460 Datasheet(HTML) 23 Page - Analog Devices

Similar Part No. - AD9460_15

Similar Description - AD9460_15

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL