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AD9460 Datasheet(PDF) 11 Page - Analog Devices

Part # AD9460
Description  16-Bit, 80 MSPS/105 MSPS ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9460 Datasheet(HTML) 11 Page - Analog Devices

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AD9460
Rev. 0 | Page 11 of 32
Pin No.
Mnemonic
Description
11
REFB
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT (Pin
10) with 0.1 μF and 10 μF capacitors.
12 to 17, 25 to 31, 35, 37
AVDD2
5.0 V Analog Supply (±5%).
22
VIN+
Analog Input—True.
23
VIN−
Analog Input—Complement.
40
CLK+
Clock Input—True.
41
CLK−
Clock Input—Complement.
47, 63, 75, 87
DRGND
Digital Output Ground.
48, 64, 76, 88
DRVDD
3.3 V Digital Output Supply (3.0 V to 3.6 V).
67
DCO−
Data Clock Output—Complement.
68
DCO+
Data Clock Output—True.
70
D0+ (LSB)
D0 True Output Bit (CMOS Levels).
71
D1+
D1 True Output Bit.
72
D2+
D2 True Output Bit.
73
D3+
D3 True Output Bit.
74
D4+
D4 True Output Bit.
77
D5+
D5 True Output Bit.
78
D6+
D6 True Output Bit.
79
D7+
D7 True Output Bit.
80
D8+
D8 True Output Bit.
81
D9+
D9 True Output Bit.
82
D10+
D10 True Output Bit.
83
D11+
D11 True Output Bit.
84
D12+
D12 True Output Bit.
85
D13+
D13 True Output Bit.
86
D14+
D14 True Output Bit.
89
D15+ (MSB)
D15 True Output Bit.
90
OR+
Out-of-Range True Output Bit.
100
SFDR
SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed
grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for
optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the
AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.


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