AD9020

–10–

REV. C

ANALOG

INPUT

N

ENCODE

DATA

OUTPUT

N + 1

N + 1

DATA FOR N

DATA FOR N + 1

t

a

t

OD

t

t

N

N

Figure 9. Timing Diagram

Timing

In the AD9020, the rising edge of the ENCODE signal triggers

the A/D conversion by latching the comparators. (See Figure 9.)

The ENCODE is TTL/CMOS-compatible and should be driven

from a low jitter (phase noise) source. Jitter on the ENCODE

signal will raise the noise floor of the converter. Fast, clean edges

will reduce the jitter in the signal and allow optimum ac perfor-

mance. Locking the system clock to a crystal oscillator also

helps reduce jitter. The AD9020 is designed to operate with a

50% duty cycle; small (10%) variations in duty cycle should not

degrade performance.

Data Format

INVERT and LSBs INVERT pins. These inputs are dc control

gives information to choose from among Binary, Inverted Binary,

Two’s Complement and Inverted Two’s Complement coding.

The OVERFLOW output is an indication that the analog input

overflow transition voltage and output delay are not tested or

included in the data sheet limits. Performance of the overflow

indicator is dependent on circuit layout and slew rate of the

encode signal. The operation of this function does not affect the

requiring a critical measure of the analog input voltage.

Layout and Power Supplies

Proper layout of high speed circuits is always critical but par-

ticularly important when both analog and digital signals

are involved.

Analog signal paths should be kept as short as possible and be

properly terminated to avoid reflections. The analog input volt-

age and the voltage references should be kept away from digital

signal paths; this reduces the amount of digital switching noise

that is capacitively coupled into the analog section of the circuit.

Digital signal paths should also be kept short, and run lengths

should be matched to avoid propagation delay mismatch.

In high-speed circuits, layout of the ground circuit is a critical fac-

tor. A single, low impedance ground plane, on the component

side of the board, will reduce noise on the circuit ground. Power

supplies should be capacitively coupled to the ground plane to

reduce noise in the circuit. Multilayer boards allow designers to

lay out signal traces without interrupting the ground plane and

provide low impedance power planes.

It is especially important to maintain the continuity of the ground

plane under and around the AD9020. In systems with dedicated

digital and analog grounds, all grounds of the AD9020 should be

connected to the analog ground plane.

lated from the supplies used for external devices; this further reduces

the amount of noise coupled into the A/D converter. Sockets limit

the dynamic performance and should be used only for prototypes or

evaluation—PCK Elastomerics Part # CCS-68-55 is recommended

for the LCC package.

An evaluation board is available to aid designers and provide a

suggested layout.