CDP1855 datasheet(11/15 Pages) INTERSIL

Part #	CDP1855

Description	8-Bit Programmable Multiply/Divide Unit

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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11 / 15 page

4-57

Y

3Y2Y1Z3Z2Z1

X

3X2X1

--------------------------------------------

Z

3Z2Z1

=

Y

3Y2Y1

X

3X2X1

----------------------

+

FIGURE 5. CASCADING THREE MDU’s (CDP1855) IN AN 1800 SYSTEM WITH MDU’s BEING ACCESSED AS I/O PORTS IN

PROGRAMMING EXAMPLE

FIGURE 6. CASCADING FOUR MDU’s (CDP1855)

C.I.

ZR

YR

RA2

RA1

RA0

CTL

CE

CLR

STB

RD/

BUS

CDP1855

C.O.

ZL

YL

SHIFT

CLK

CN0

CN1

WE

VDD

DATA BUS

C.I.

ZR

YR

RA2

RA1

RA0

CTL

CE

CLR

STB

RD/

BUS

CDP1855

C.O.

ZL

YL

SHIFT

CLK

CN0

CN1

WE

VDD

C.I.

ZR

YR

RA2

RA1

RA0

CTL

CE

CLR

STB

RD/

BUS

CDP1855

O.F.

ZL

YL

SHIFT

CLK

CN0

CN1

WE

VDD

EF1

BUS

MRD

TPB

CLEAR

N2

N1

N0

MOST SIGNIFICANT

LEAST SIGNIFICANT

OR

VDD

I/O SELECT

88

8

CLOCK

8

TO

CPU

C.I.

ZR

YR

RA2

RA1

RA0

CTL

CE

CLR

STB

RD/

BUS

CDP1855

C.O.

ZL

YL

SHIFT

CLK

CN0

CN1

WE

VDD

DATA BUS

C.I.

ZR

YR

RA2

RA1

RA0

CTL

CE

CLR

STB

RD/

BUS

CDP1855

C.O.

ZL

YL

SHIFT

CLK

CN0

CN1

WE

VDD

C.I.

ZR

YR

RA2

RA1

RA0

CTL

CE

CLR

STB

RD/

BUS

CDP1855

C.O.

ZL

YL

SHIFT

CLK

CN0

CN1

WE

C.I.

ZR

YR

RA2

RA1

RA0

CTL

CE

CLR

STB

RD/

BUS

CDP1855

O.F.

ZL

YL

SHIFT

CLK

CN0

CN1

WE

VDD

CLOCK

EF1

BUS

MRD

TPB

CLEAR

N2

N1

N0

MOST SIGNIFICANT

LEAST SIGNIFICANT

CDP1855, CDP1855C

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CDP1855 Datasheet(PDF) 11 Page - Intersil Corporation

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