7-473

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4502BMS

CMOS Strobed Hex Inverter/Buffer

Features

• High Voltage Type (20V Rating)

• 2 TTL Load Output Drive Capability

• 3 State Outputs

• Common Output Disable Control

• Inhibit Control

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• 3 State Hex Inverter for Interfacing ICs with Data

Buses

• COS/MOS to TTL Hex Buffer

Description

CD4502BMS consists of six inverter/buffers with 3 state

outputs. A logic “1” on the OUTPUT DISABLE input

produces a high impedance state in all six outputs. This

feature permits common busing of the outputs, thus

simplifying system design. A Logic “1” on the INHIBIT input

switches all six outputs to logic “0” if the OUTPUT DISABLE

input is a logic “0”. This device is capable of driving two

standard TTL loads, which is equivalent to six times the

JEDEC “B” series IOL standard.

The CD4502BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

H4T

Frit Seal DIP

H1F

Ceramic Flatpack

H6W

December 1992

File Number

3334

Pinout

CD4502BMS

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

D3

Q3

D1

3 STATE

Q1

D2

VSS

Q2

VDD

Q6

D5

INHIBIT

Q5

D4

Q4

D6

OUTPUT DISABLE

Q2

Q1

7

5

4

3 STATE

VDD = 16

VSS = 8

OUTPUT DISABLE

D2

D1

6

3

INHIBIT

12

Q3

2

D3

1

Q4

9

D4

10

Q5

11

D5

13

Q6

14

D6

15