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CD4502BMS Datasheet(PDF) 4 Page - Intersil Corporation

Part # CD4502BMS
Description  CMOS Strobed Hex Inverter/Buffer
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4502BMS Datasheet(HTML) 4 Page - Intersil Corporation

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Specifications CD4502BMS
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2, 4
+125oC
5.4
-
mA
-55oC
9.6
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2, 4
+125oC
14.4
-
mA
-55oC
25.2
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
+25oC, +125oC,
-55oC
-3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
+25oC, +125oC,
-55oC
+7
-
V
Propagation Delay
Data to Output
TPHL1
VDD = 10V
1, 2, 3
+25oC
-
120
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
Propagation Delay
Data to Output
TPLH1
VDD = 10V
1, 2, 3
+25oC
-
180
ns
VDD = 15V
1, 2, 3
+25oC
-
130
ns
Propagation Delay
Inhibit to Output
TPHL2
VDD = 10V
1, 2, 3
+25oC
-
120
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
Propagation Delay
Inhibit to Output
TPLH2
VDD = 10V
1, 2, 3
+25oC
-
180
ns
VDD = 15V
1, 2, 3
+25oC
-
130
ns
Propagation Delay
Disable to Output
TPHZ
VDD = 10V
1, 2, 4
+25oC
-
80
ns
VDD = 15V
1, 2, 4
+25oC
-
60
ns
Propagation Delay
Disable to Output
TPZH
VDD = 10V
1, 2, 4
+25oC
-
100
ns
VDD = 15V
1, 2, 4
+25oC
-
80
ns
Propagation Delay
Disable to Output
TPLZ
VDD = 10V
1, 2, 4
+25oC
-
130
ns
VDD = 15V
1, 2, 4
+25oC
-
110
ns
Propagation Delay
Disable to Output
TPZL
VDD = 10V
1, 2, 4
+25oC
-
110
ns
VDD = 15V
1, 2, 4
+25oC
-
80
ns
Transition Time
TTHL
VDD = 10V
1, 2, 3
+25oC
-
60
ns
VDD = 15V
1, 2, 3
+25oC
-
40
ns
Transition Time
TTLH
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
Input Capacitance
CIN
Any Inputs
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX


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