7-455

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4070BMS

CD4077BMS

CMOS Quad Exclusive OR and

Exclusive NOR Gates

Pinouts

CD4070BMS

TOP VIEW

CD4077BMS

TOP VIEW

Functional Diagram

CD4070BMS

CD4077BMS

A

B

J = A

⊕B

K = C

⊕D

C

D

VSS

VDD

H

G

M = G

⊕H

L = E

⊕F

F

E

1

2

3

4

5

6

7

14

13

12

11

10

9

8

A

B

J = A

K = C

C

D

VSS

VDD

H

G

M = G

L = E

F

E

1

2

3

4

5

6

7

14

13

12

11

10

9

8

A

B

C

D

E

F

G

H

1

2

5

6

8

9

12

13

3

4

10

11

J = A

⊕B

K = C

⊕D

M = G

⊕H

L = E

⊕F

VSS = 7

VDD = 14

J

K

L

M

A

B

C

D

E

F

G

H

1

2

5

6

8

9

12

13

3

4

10

11

J = A

K = C

M = G

L = E

J

K

L

M

Features

• High Voltage Types (20V Rating)

• CD4070BMS - Quad Exclusive OR Gate

• CD4077BMS - Quad Exclusive NOR Gate

• Medium Speed Operation

- tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF

• 5V, 10V and 15V Parametric Ratings

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Logical Comparators

• Parity Generators and Checkers

• Adders/Subtractors

Description

CD4070BMS contains four independent Exclusive OR gates.

The CD4077BMS contains four independent Exclusive NOR

gates.

The CD4070BMS and CD4077BMS provide the system

designer with a means for direct implementation of the

Exclusive OR and Exclusive NOR functions, respectively.

The CD4070BMS and CD4077BMS are supplied in these 14

lead outline packages:

Braze Seal DIP

H4Q

Frit Seal DIP

H1B

Ceramic Flatpack

*H4F

†H3W

*CD4070B Only

†CD4077B Only

File Number

3322

December 1992