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AD7707 Datasheet(PDF) 30 Page - Analog Devices |
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AD7707 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 52 page  AD7707 Rev. B | Page 30 of 52 CALIBRATION The AD7707 provides a number of calibration options that can be programmed via the MD1 and MD0 bits of the setup register. The different calibration options are outlined in the Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 section and the Calibration Sequences section. A calibration cycle can be initiated at any time by writing to these bits of the setup register. Calibration on the AD7707 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch, or bipolar/unipolar input range. The AD7707 offers self-calibration and system calibration facili- ties. For full calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are zero-scale and full-scale points. These points are derived by performing a conversion on the different input voltages provided to the input of the modula- tor during calibration. As a result, the accuracy of the calibration can only be as good as the noise level that it provides in normal mode. The result of the zero-scale calibration conversion is stored in the zero-scale calibration register whereas the result of the full-scale calibration conversion is stored in the full-scale calibration register. With these readings, the microcontroller can calculate the offset and the gain slope for the input-to- output transfer function of the converter. SELF-CALIBRATION A self-calibration is initiated on the AD7707 by writing the appropriate values (0, 1) to the MD1 and MD0 bits of the setup register. In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (that is, AIN1 = LOCOM = internal bias voltage in the case of the AD7707. The PGA is set for the selected gain (as per the G2, G1, and G0 bits in the setup register) for this zero-scale calibration conversion. The full- scale calibration conversion is performed at the selected gain on an internally-generated voltage of VREF/selected gain. The duration time for the calibration is 6 × 1/output rate. This is made up of 3 × 1/output rate for the zero-scale calibration and 3 × 1/output rate for the full-scale calibration. At this time, the MD1 and MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 × 1/output rate. This is made up of 3 × 1/output rate for the zero-scale calibration, 3 × 1/output rate for the full-scale calibration, 3 × 1/output rate for a conversion on the analog input, and some overhead to correctly set up the coefficients. If DRDY is low before (or goes low during) the calibration command write to the setup register, it may take up to one modulator cycle (MCLK IN/ 128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as in the previous case but because the part is configured for bipolar operation, the shorted inputs point is actually midscale of the transfer function. Errors due to resistor mismatch in the attenuator on the high level input channel AIN3 are not removed by a self-calibration. SYSTEM CALIBRATION System calibration allows the AD7707 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as self- calibration, but uses voltage values presented by the system to the AIN inputs for the zero-scale and full-scale points. Full system calibration requires a two-step process, a ZS system calibration followed by an FS system calibration. For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated, and remain stable until the step is complete. Once the system zero-scale voltage has been set up, a ZS system calibration is then initiated by writing the appropriate values (1, 0) to the MD1 and MD0 bits of the setup register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. At this time, the MD1 and MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/output rate as the part performs a normal conversion on the analog input voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the etup egister, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. After the zero-scale point is calibrated, the full-scale point is applied to the analog input and the second step of the calibration process is initiated by again writing the appropriate values (1, 1) to MD1 and MD0. Again, the full-scale voltage must be set up before the calibration is initiated and it must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. At this time, the MD1 and |
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