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AD7707 Datasheet(PDF) 33 Page - Analog Devices |
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AD7707 Datasheet(HTML) 33 Page - Analog Devices |
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33 / 52 page  AD7707 Rev. B | Page 33 of 52 USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT The AD7707 requires a master clock input, which can be an external CMOS compatible clock signal applied to the MCLK IN pin with the MCLK OUT pin left unconnected. Alternatively, a crystal or ceramic resonator of the correct frequency can be connected between MCLK IN and MCLK OUT as shown in Figure 18, in which case the clock circuit functions as an oscilla- tor, providing the clock source for the part. The input sampling frequency, the modulator sampling frequency, the −3 dB fre- quency, output update rate, and calibration time are all directly related to the master clock frequency, fCLKIN. Reducing the master clock frequency by a factor of 2 halves these frequencies and update rate, and doubles the calibration time. The current drawn from the DVDD power supply is also related to fCLKIN. Reducing fCLKIN by a factor of 2 halves the DVDD current but does not affect the current drawn from the AVDD. MCLK IN MCLK OUT C1 C2 AD7707 CRYSTAL OR CERAMIC RESONATOR Figure 18. Crystal/Resonator Connection for the AD7707 Using the part with a crystal or ceramic resonator between the MCLK IN and MCLK OUT pins generally causes more current to be drawn from DVDD than when the part is clocked from a driven clock signal at the MCLK IN pin. This is because the on- chip oscillator circuit is active in the case of the crystal or ceramic resonator. Therefore, the lowest possible current on the AD7707 is achieved with an externally applied clock at the MCLK IN pin with MCLK OUT unconnected, unloaded, and disabled. The amount of additional current taken by the oscillator depends on a number of factors—first, the larger the value of capacitor (C1 and C2) placed on the MCLK IN and MCLK OUT pins, the larger the current consumption on the AD7707. Care should be taken not to exceed the capacitor values recommended by the crystal and ceramic resonator manufacturers to avoid consuming unnecessary current. Typical values for C1 and C2 are recom- mended by crystal or ceramic resonator manufacturers; these are in the range of 30 pF to 50 pF. If the capacitor values on MCLK IN and MCLK OUT are kept in this range, they do not result in any excessive current. Another factor that influences the current is the effective series resistance (ESR) of the crystal that appears between the MCLK IN and MCLK OUT pins of the AD7707. As a general rule, the lower the ESR value is, the lower the current taken by the oscillator circuit. When operating with a clock frequency of 2.4576 MHz, there is 50 μA difference in the current between an externally applied clock and a crystal resonator when operating with a DVDD of 3 V. With DVDD = 5 V and fCLKIN = 2.4576 MHz, the typical current increases by 250 μA for a crystal/resonator supplied clock vs. an externally applied clock. The ESR values for crystals and resonators at this frequency tend to be low and, as a result there tends to be little difference between different crystal and resonator types. When operating with a clock frequency of 1 MHz, the ESR value for different crystal types varies significantly. As a result, the current drain varies across crystal types. When using a crystal with an ESR of 700 Ω or when using a ceramic resonator, the increase in the typical current over an externally applied clock is 20 μA with DVDD = 3 V and 200 μA with DVDD = 5 V. When using a crystal with an ESR of 3 kΩ, the increase in the typical current over an externally applied clock is again 100 μA with DVDD = 3 V but 400 μA with DVDD = 5 V. The on-chip oscillator circuit also has a start-up time associated with it before it is oscillating at its correct frequency and correct voltage levels. Typical start-up times with DVDD = 5 V are 6 ms using a 4.9512 MHz crystal, 16 ms with a 2.4576 MHz crystal and 20 ms with a 1 MHz crystal oscillator. Start-up times are typically 20% slower when the power supply voltage is reduced to 3 V. At 3 V supplies, depending on the loading capacitances on the MCLK pins, a 1 MΩ feedback resistor may be required across the crystal or resonator to keep the start-up times around the 20 ms duration. The AD7707’s master clock appears on the MCLK OUT pin of the device. The maximum recommended load on this pin is one CMOS load. When using a crystal or ceramic resonator to generate the AD7707’s clock, it may be desirable to use this clock as the clock source for the system. In this case, it is recommended that the MCLK OUT signal is buffered with a CMOS buffer before being applied to the rest of the circuit. SYSTEM SYNCHRONIZATION The FSYNC bit of the setup register allows the user to reset the modulator and digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, when the FSYNC is changed from 1 to 0. With a 1 in the FSYNC bit of the setup register, the digital filter and analog modulator are held in a known reset state and the part is not processing any input samples. When a 0 is then written to the FSYNC bit, the modulator and filter are taken out of this reset state and the part starts to gather samples again on the next master clock edge. The FSYNC input can also be used as a software start convert command allowing the AD7707 to be operated in a conventional converter fashion. In this mode, writing to the FSYNC bit starts conversion and the falling edge of DRDY indicates when con- version is complete. The disadvantage of this scheme is that the settling time of the filter has to be taken into account for every data register update. This means that the rate at which the data register is updated is three times slower in this mode. |
Similar Part No. - AD7707_15 |
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Similar Description - AD7707_15 |
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