 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD7612 Datasheet(PDF) 29 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD7612 Datasheet(HTML) 29 Page - Analog Devices |
|
|
29 / 32 page  Data Sheet AD7612 Rev. A | Page 29 of 32 HARDWARE CONFIGURATION The AD7612 can be configured at any time with the dedicated hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/2C, and PD for parallel mode (SER/PAR = low) or serial hardware mode (SER/ PAR = high, HW/SW = high). Programming the AD7612 for mode selection and input range configuration can be done before or during conversion. Like the RESET input, the ADC requires at least one acquisition time to settle as indicated in Figure 44. See Table 6 for pin descriptions. Note that these inputs are high impedance when using the software configuration mode. SOFTWARE CONFIGURATION The pins multiplexed on D[15:12] used for software configura- tion are: HW/SW, SCIN, SCCLK, and SCCS. The AD7612 is programmed using the dedicated write-only serial configurable port (SCP) for conversion mode, input range selection, output coding, and power-down using the serial configuration register. See Table 9 for details of each bit in the configuration register. The SCP can only be used in serial software mode selected with SER/PAR = high and HW/SW = low since the port is multiplexed on the parallel interface. The SCP is accessed by asserting the port’s chip select, SCCS, and then writing SCIN synchronized with SCCLK, which (like SDCLK) is edge sensitive depending on the state of INVSCLK. See Figure 45 for timing details. SCIN is clocked into the con- figuration register MSB first. The configuration register is an internal shift register that begins with Bit 8, the start bit. The 9th SPPCLK edge updates the register and allows the new settings to be used. As indicated in the timing diagram, at least one acquisition time is required from the 9th SCCLK edge. Bits [1:0] are reserved bits and are not written to while the SCP is being updated. The SCP can be written to at any time, up to 40 MHz, and it is recommended to write to while the AD7612 is not busy convert- ing, as detailed in Figure 45. In this mode, the full 750 kSPS is not attainable because the time required for SCP access is (t31 + 8 × 1/ SCCLK +t8) minimum. If the full throughput is required, the SCP can be written to during conversion, however it is not recommended to write to the SCP during the last 475 ns of con- version (BUSY = high) or performance degradation can result. In addition, the SCP can be accessed in both serial master and serial slave read during and read after convert modes. Note that at power up, the configuration register is undefined. The RESET input clears the configuration register (sets all bits to 0), thus placing the configuration to 0 V to 5 V input, normal mode, and twos complemented output. Table 9. Configuration Register Description Bit Name Description 8 START START bit. With the SCP enabled (SCCS = low), when START is high, the first rising edge of SCCLK (INVSCLK = low) begins to load the register with the new configuration. 7 BIPOLAR Input Range Select. Used in conjunction with Bit 6, TEN, per the following: Input Range BIPOLAR TEN 0 V to 5 V Low Low 0 V to 10 V Low High ±5 V High Low ±10 V Low High 6 TEN Input Range Select. See Bit 7, BIPOLAR. 5 PD Power Down. PD = Low, normal operation. PD = High, power down the ADC. The SCP is accessi- ble while in power down. To power up the ADC, write PD = low on the next configuration setting. 4 IMPULSE Mode Select. Used in conjunction with Bit 3, WARP per the following: Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High 3 WARP Mode Select. See Bit 4, IMPULSE. 2 OB/2C Output Coding OB/2C = Low, use twos complement output. OB/2C = High, use straight binary output. 1 RSV Reserved. 0 RSV Reserved. WARP, IMPULSE BUSY HW/SW = 0 CNVST BIPOLAR, TEN t8 SER/PAR = 0, 1 PD = 0 t8 Figure 44. Hardware Configuration Timing |
Similar Part No. - AD7612_15 |
|
Similar Description - AD7612_15 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
