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AD7612 Datasheet(PDF) 27 Page - Analog Devices |
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AD7612 Datasheet(HTML) 27 Page - Analog Devices |
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27 / 32 page  Data Sheet AD7612 Rev. A | Page 27 of 32 SLAVE SERIAL INTERFACE The pins multiplexed on D[11:4] used for slave serial interface are: EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK and RDERROR. External Clock (SER/PAR = High, EXT/INT = High) Setting the EXT/INT = high allows the AD7612 to accept an externally supplied serial data clock on the SDCLK pin. In this mode, several methods can be used to read the data. The exter- nal serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. A clock can be either normally high or normally low when inactive. For detailed timing diagrams, see Figure 42 and Figure 43. While the AD7612 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins, or degradation of the conversion result may occur. This is par- ticularly important during the last 475 ns of the conversion phase because the AD7612 provides error correction circuitry that can correct for an improper bit decision made during the first part of the conversion phase. For this reason, it is recommended that any external clock provided, is a discontinuous clock that transi- tions only when BUSY is low, or, more importantly, that it does not transition during the last 475 ns of BUSY high. External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 42 shows the detailed timing diagrams for this method. After a conversion is complete, indicated by BUSY returning low, the conversion result can be read while both CS and RD are low. Data is shifted out MSB first with 16 clock pulses and, depending on the SDCLK frequency, can be valid on the falling and rising edges of the clock. One advantage of this method is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 40 MHz, which accommodates both the slow digital host interface and the fastest serial reading. Daisy-Chain Feature Also in the read after convert mode, the AD7612 provides a daisy- chain feature for cascading multiple converters together using the serial data input, SDIN, pin. This feature is useful for reduce- ing component count and wiring connections when desired, for instance, in isolated multiconverter applications. See Figure 42 for the timing details. An example of the concatenation of two devices is shown in Figure 41. Simultaneous sampling is possible by using a common CNVST signal. Note that the SDIN input is latched on the opposite edge of SDCLK used to shift out the data on SDOUT (SDCLK falling edge when INVSCLK = low). Therefore, the MSB of the upstream converter follows the LSB of the downstream con- verter on the next SDCLK cycle. In this mode, the 40 MHz SDCLK rate cannot be used since the SDIN to SDCLK setup time, t33, is less than the minimum time specified. (SDCLK to SDOUT delay, t32, is the same for all converters when simul- taneously sampled). For proper operation, the SDCLK edge for latching SDIN (or ½ period of SDCLK) needs to be: 33 32 SDCLK t t t 2 / 1 Or the max SDCLK frequency needs to be: ) ( 2 1 33 32 SDCLK t t f If not using the daisy-chain feature, the SDIN input should be tied either high or low. SCLK SDOUT RDC/SDIN AD7612 #1 (DOWNSTREAM) AD7612 #2 (UPSTREAM) BUSY OUT BUSY BUSY DATA OUT SCLK RDC/SDIN SDOUT SCLK IN CNVST IN CNVST CS CNVST CS CS IN Figure 41. Two AD7612 Devices in a Daisy-Chain Configuration External Clock Data Read During Previous Conversion Figure 43 shows the detailed timing diagrams for this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. Data is shifted out MSB first with 16 clock pulses and, depending on the SDCLK frequency, can be valid on the falling and rising edges of the clock. The 16 bits have to be read before the current conversion is complete; otherwise, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. To reduce performance degradation due to digital activity, a fast discontinuous clock of at least 40 MHz is recommended to ensure that all the bits are read during the first half of the SAR conversion phase. The daisy-chain feature should not be used in this mode since digital activity occurs during the second half of the SAR conversion phase likely resulting in performance degradation. |
Similar Part No. - AD7612_15 |
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Similar Description - AD7612_15 |
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