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AD7612 Datasheet(PDF) 23 Page - Analog Devices |
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AD7612 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 32 page  Data Sheet AD7612 Rev. A | Page 23 of 32 Power Sequencing The AD7612 requires sequencing of the AVDD and DVDD supplies. AVDD should come up prior to or simultaneously with DVDD. This can be achieved using the configuration in Figure 27 or sequencing the supplies in that manner. The other supplies can be sequenced as desired as long as absolute maximum ratings are observed. The AD7612 is very insensitive to power supply variations on AVDD over a wide frequency range, as shown in Figure 31. 80 75 1 10000 FREQUENCY (kHz) 10 100 1000 70 65 60 55 50 45 40 35 30 EXT REF INT REF Figure 31. AVDD PSRR vs. Frequency Power Dissipation vs. Throughput In impulse mode, the AD7612 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced (see Figure 32). This feature makes the AD7612 ideal for very low power, battery-operated applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, OVDD and OGND). 1000 1 1 1000 SAMPLING RATE (kSPS) 10 100 10 100 WARP MODE POWER IMPULSE MODE POWER PDREF = PDBUF = HIGH Figure 32. Power Dissipation vs. Sample Rate Power Down Setting PD = high powers down the AD7612, thus reducing supply currents to their minimums as shown in Figure 23. When the ADC is in power down, the current conversion (if any) is completed and the digital bus remains active. To further reduce the digital supply currents, drive the inputs to OVDD or OGND. Power down can also be programmed with the configuration register. See the Software Configuration section for details. Note that when using the configuration register, the PD input is a don’t care and should be tied to either high or low. CONVERSION CONTROL The AD7612 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown in Figure 33. Once initiated, it cannot be restarted or aborted, even by the power-down input, PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. BUSY MODE CONVERT ACQUIRE ACQUIRE CONVERT CNVST t1 t2 t4 t3 t5 t6 t7 t8 Figure 33. Basic Conversion Timing Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot, undershoot, or ringing. The CNVST trace should be shielded with ground and a low value (such as 50 Ω) serial resistor termination should be added close to the output of the component that drives this line. For applications where SNR is critical, the CNVST signal should have very low jitter. This can be achieved by using a dedicated oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 27. |
Similar Part No. - AD7612_15 |
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Similar Description - AD7612_15 |
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