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AD7612 Datasheet(PDF) 17 Page - Analog Devices |
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AD7612 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 32 page  Data Sheet AD7612 Rev. A | Page 17 of 32 THEORY OF OPERATION SWA SWB IN+ REF REFGND LSB MSB 32,768C IN– 16,384C 4C 2C C C 65,536C CONTROL LOGIC SWITCHES CONTROL BUSY OUTPUT CODE CNVST COMP Figure 25. ADC Simplified Schematic OVERVIEW The AD7612 is a very fast, low power, precise, 16-bit analog-to- digital converter (ADC) using successive approximation capacitive digital-to-analog (CDAC) architecture. The AD7612 can be configured at any time for one of four input ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write only, SPI-compatible interface via a configuration register in serial software mode. The AD7612 uses Analog Device’s patented iCMOS high voltage process to accommodate 0 to 5 V, 0 to 10 V, ±5 V, and ±10 V input ranges without the use of conventional thin films. Only one acquisition cycle, t8, is required for the inputs to latch to the correct configuration. Resetting or power cycling is not required for reconfiguring the ADC. The AD7612 features different modes to optimize performance according to the applications. It is capable of converting 750,000 samples per second (750 kSPS) in warp mode, 600 kSPS in normal mode, and 500 kSPS in impulse mode. The AD7612 provides the user with an on-chip track-and-hold, successive approximation ADC that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. For unipolar input ranges, the AD7612 typically requires three supplies; VCC, AVDD (which can supply DVDD), and OVDD which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. For bipolar input ranges, the AD7612 requires the use of the additional VEE supply. The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP 7 mm × 7 mm packages that combine space savings with flexi- bility. In addition, the AD7612 can be configured as either a parallel or serial SPI-compatible interface. CONVERTER OPERATION The AD7612 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is complete and the CNVST input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 through VREF/ 65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings the BUSY output low. |
Similar Part No. - AD7612_15 |
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Similar Description - AD7612_15 |
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