AD5662_15 datasheet(15/24 Pages) AD

Part #	AD5662

Description	2.7 V to 5.5 V, 250 A, Rail-to-Rail Output 16-Bit nanoDACT in a SOT-23

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AD5662

Rev. A | Page 15 of 24

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 34). The first

six bits are don’t cares. The next two are control bits that control

the part’s mode of operation (normal mode or any one of three

power-down modes). See the Power-Down Modes section for a

more complete description of the various modes. The next 16

bits are the data bits. These are transferred to the DAC register

on the 24th falling edge of SCLK.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 24 falling edges of SCLK, and the DAC is updated on the

24th falling edge. However, if SYNC is brought high before the

24th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see

).

Figure 35

POWER-ON RESET

The AD5662 family contains a power-on reset circuit that

controls the output voltage during power-up. The AD5662x-1

DAC output powers up to 0 V, and the AD5662x-2 DAC output

powers up to midscale. The output remains there until a valid

write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the

output of the DAC while it is in the process of powering up.

DATA BITS

DB23 (MSB)

PD1

PD0

D15

D14

D13

D12

X

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

DBO (LSB)

D1

D0

NORMAL OPERATION

1 k

Ω TO GND

100 k

Ω TO GND

THREE-STATE

POWER-DOWN MODES

0

1

0

1

0

1

Figure 34. Input Register Contents

DIN

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24TH FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24TH FALLING EDGE

SYNC

SCLK

Figure 35. SYNC Interrupt Facility

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