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AB28F200BX-T90 Datasheet(PDF) 28 Page - Intel Corporation |
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AB28F200BX-T90 Datasheet(HTML) 28 Page - Intel Corporation |
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28 / 33 page  A28F200BX-TB AC CHARACTERISTICS For WE -Controlled Write Operations(1) Versions(4) A28F200BX-90(9) Unit Symbol Parameter Notes Min Max tAVAV tWC Write Cycle Time 90 ns tPHWL tPS RP High Recovery to 210 ns WE Going Low tELWL tCS CE Setup to WE Going Low 0 ns tPHHWH tPHS RP VHH Setup to WE Going High 6 8 100 ns tVPWH tVPS VPP Setup to WE Going High 5 8 100 ns tAVWH tAS Address Setup to WE Going High 3 60 ns tDVWH tDS Data Setup to WE Going High 4 60 ns tWLWH tWP WE Pulse Width 60 ns tWHDX tDH Data Hold from WE High 4 0 ns tWHAX tAH Address Hold from WE High 3 10 ns tWHEH tCH CE Hold from WE High 10 ns tWHWL tWPH WE Pulse Width High 30 ns tWHQV1 Duration of WordByte 2 5 7 m s Write Operation tWHQV2 Duration of Erase Operation (Boot) 2 5 6 04 s tWHQV3 Duration of Erase 2 5 04 s Operation (Parameter) tWHQV4 Duration of Erase Operation (Main) 2 5 6 07 s tQWL tVPH VPP Hold from Valid SRD 5 8 0 ns tQVPH tPHH RP VHH Hold from Valid SRD 6 8 0 ns tPHBR Boot-Block Relock Delay 7 8 100 ns NOTES 1 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC Characteristics during Read Mode 2 The on-chip WSM completely automates programerase operations programerase algorithms are now controlled inter- nally which includes verify and margining operations 3 Refer to command definition table for valid AIN 4 Refer to command definition table for valid DIN 5 ProgramErase durations are measured to valid SRD data (successful operation SR7e1) 6 For Boot Block ProgramErase RP should be held at VHH until operation completes successfully 7 Time tPHBR is required for successful relocking of the Boot Block 8 Sampled but not 100% tested 9 See Standard Test Configuration 28 |
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