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AB28F200BX-T90 Datasheet(PDF) 21 Page - Intel Corporation |
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AB28F200BX-T90 Datasheet(HTML) 21 Page - Intel Corporation |
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21 / 33 page  A28F200BX-TB 344 RESETDEEP POWER-DOWN The 2-Mbit boot block flash family has a RP pin which places the device in the deep power-down mode When RP is at a logic-low (GND g02V) all circuits are turned off and the device typically draws a maximum 80 mAofVCC current During read modes the RP pin going low dese- lects the memory and places the output drivers in a high impedance state Recovery from the deep pow- er-down state requires a minimum of 300 ns to ac- cess valid data (tPHQV) During erase or program modes RP low will abort either erase or program operation The contents of the memory are no longer valid as the data has been corrupted by the RP function As in the read mode above all internal circuitry is turned off to achieve the low current level RP transitions to VIL or turning power off to the device will clear the status register This use of RP during system reset is important with automated writeerase devices When the sys- tem comes out of reset it expects to read from the flash memory Automated flash memories provide status information when accessed during write erase modes If a CPU reset occurs with no flash memory reset proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data Intel’s Flash Memories allow proper CPU initialization fol- lowing a system reset through the use of the RP input In this application RP is controlled by the same RESET signal that resets the system CPU 35 Power-Up Operation The 2-Mbit boot block flash family is designed to offer protection against accidental block erasure or programming during power transitions Upon power- up the 2-Mbit boot block flash family is indifferent as to which power supply VPP or VCC powers-up first Power suppy sequencing is not required The 2-Mbit boot block flash family ensures the CUI is reset to the read mode on power-up In addition on power-up the user must either drop CE low or present a new address to ensure valid data at the outputs A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active Since both WE and CE must be low for a command write driving either signal to VIH will inhibit writes to the device The CUI architecture provides an added level of protection since alteration of mem- ory contents can only occur after successful com- pletion of the two-step command sequences Final- ly the device is disabled until RP is brought to VIH regardless of the state of its control inputs This fea- ture provides yet another level of memory protec- tion 36 Power Supply Decoupling Flash memory’s power switching characteristics re- quire careful device decoupling methods System designers are interested in 3 supply current issues Standby current levels (ICCS) Active current levels (ICCR) Transient peaks produced by falling and rising edges of CE Transient current magnitudes depend on the device outputs’ capacitive and inductive loading Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks Each flash device should have a 01 mF ceramic capacitor connected between each VCC and GND and be- tween its VPP and GND These high frequency low- inherent inductance capacitors should be placed as close as possible to the package leads 361 VPP TRACE ON PRINTED CIRCUIT BOARDS Writing to flash memories while they reside in the target system requires special consideration of the VPP power supply trace by the printed circuit board designer The VPP pin supplies the flash memory cell’s current for programming and erasing One should use similar trace widths and layout consider- ations given to the VCC power supply trace Ade- quate VPP supply traces and decoupling will de- crease spikes and overshoots 362 VCC VPP AND RP TRANSITIONS The CUI latches commands as issued by system software and is not altered by VPP or CE tran- sitions or WSM actions Its state upon power-up af- ter exit from deep power-down mode or after VCC transitions below VLKO (Lockout voltage) is Read Array mode After any wordbyte write or block erase operation is complete and even after VPP transitions down to VPPL the CUI must be reset to Read Array mode via the Read Array command when accesses to the flash memory are desired 21 |
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