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AB28F200BX-T90 Datasheet(PDF) 19 Page - Intel Corporation |
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AB28F200BX-T90 Datasheet(HTML) 19 Page - Intel Corporation |
19 / 33 page ![]() A28F200BX-TB 290500 – 9 Bus Command Comments Operation Write Setup Data e 20H Erase Address e Within block to be erased Write Erase Data e D0H Address e Within block to be erased Read Status Register Data Toggle OE or CE to update Status Register Standby Check SR7 1 e Ready 0 e Busy Repeat for subsequent blocks Full status check can be done after each block or after a sequence of blocks Write FFH after the last block erase operation to reset the device to Read Array Mode Full Status Check Procedure 290500 – 10 Bus Command Comments Operation Standby Check SR3 1 e VPP Low Detect Standby Check SR45 Both 1 e Command Sequence Error Standby Check SR5 1 e Block Erase Error SR3 MUST be cleared if set during an erase attempt before further attempts are allowed by the Write State Machine SR5 is only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery Figure 8 Automated Block Erase Flowchart 19 |
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