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AB28F200BX-T90 Datasheet(PDF) 16 Page - Intel Corporation |
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AB28F200BX-T90 Datasheet(HTML) 16 Page - Intel Corporation |
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16 / 33 page  A28F200BX-TB toggling either CE or OE to determine when the program sequence is complete Only the Read Status Register command is valid while program- ming is active When programming is complete the status bits which indicate whether the program operation was successful should be checked If the programming operation was unsuccessful Bit 4 of the status regis- ter is set to a ‘‘1’’ to indicate a Program Failure lf Bit 3 is set then VPP was not within acceptable limits and the WSM will not execute the programming se- quence The status register should be cleared before at- tempting the next operation Any CUI instruction can follow after programming is completed however it must be recognized that reads from the memory status register or Intelligent Identifier cannot be ac- complished until the CUI is given the appropriate command A Read Array command must first be giv- en before memory contents can be read Figure 6 shows a system software flowchart for de- vice byte programming operation Figure 7 shows a similar flowchart for device word programming oper- ation (A28F200BX-only) 335 ERASE MODE Erasure of a single block is initiated by writing the Erase Setup and Erase Confirm commands to the CUI along with the addresses A 1216 identifying the block to be erased These addresses are latched internally when the Erase Confirm command is is- sued Block erasure results in all bits within the block being set to ‘‘1’’ The WSM will execute a sequence of internally timed events to 1 Program all bits within the block 2 Verify that all bits within the block are sufficiently programmed 3 Erase all bits within the block and 4 Verify that all bits within the block are sufficiently erased While the erase sequence is executing Bit 7 of the status register is a ‘‘0’’ When the status register indicates that erasure is complete the status bits which indicate whether the erase operation was successful should be checked If the erasure operation was unsuccessful Bit 5 of the status register is set to a ‘‘1’’ to indicate an Erase Failure If VPP was not within acceptable limits after the Erase Confirm command is issued the WSM will not execute an erase sequence instead Bit 5 of the status register is set to a ‘‘1’’ to indicate an Erase Failure and Bit 3 is set to a ‘‘1’’ to identify that VPP supply voltage was not within acceptable limits The status register should be cleared before at- tempting the next operation Any CUI instruction can follow after erasure is completed however it must be recognized that reads from the memory array status register or Intelligent Identifier can not be ac- complished until the CUI is given the appropriate command A Read Array command must first be giv- en before memory contents can be read Figure 8 shows a system software flowchart for Block Erase operation 3351 Suspending and Resuming Erase Since an erase operation typically requires 15 to 3 seconds to complete an Erase Suspend command is provided This allows erase-sequence interruption in order to read data from another block of the mem- ory Once the erase sequence is started writing the Erase Suspend command to the CUI requests that the Write State Machine (WSM) pause the erase se- quence at a predetermined point in the erase algo- rithm The status register must be read to determine when the erase operation has been suspended At this point a Read Array command can be written to the CUI in order to read data from blocks other than that which is being suspended The only other valid command at this time is the Erase Resume command or Read Status Register operation Figure 9 shows a system software flowchart detail- ing the operation During Erase Suspend mode the chip can go into a pseudo-standby mode by taking CE to VIH and the active current is now a maximum of 10 mA If the chip is enabled while in this mode by taking CE to VIL the Erase Resume command can be issued to resume the erase operation Upon completion of reads from any block other than the block being erased the Erase Resume com- mand must be issued When the Erase Resume command is given the WSM will continue with the erase sequence and complete erasing the block As with the end of erase the status register must be read cleared and the next instruction issued in or- der to continue 346 EXTENDED CYCLING Intel has designed extended cycling capability into its ETOX III flash memory technology The 2-Mbit boot block flash family is designed for 1000 pro- gramerase cycles on each of the five blocks The combination of low electric fields clean oxide pro- cessing and minimized oxide area per memory cell subjected to the tunneling electric field results in very high cycling capability 16 |
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