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AB28F200BX-T90 Datasheet(PDF) 10 Page - Intel Corporation |
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AB28F200BX-T90 Datasheet(HTML) 10 Page - Intel Corporation |
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10 / 33 page  A28F200BX-TB 2122 A28F200BX-T Memory Map The A28F200BX-T device has the 16-Kbyte boot block located from 1E000H to 1FFFFH to accommo- date those microprocessors that boot from the top of the address map In the A28F200BX-T the first 8 Kbyte parameter block resides in memory space from 1D000H to 1DFFFH The second 8-Kbyte pa- rameter block resides in memory space from 1C000H to 1CFFFH The 96-Kbyte main block re- sides in memory space from 10000H to 1BFFFH The 128-Kbyte main block resides in memory space from 00000H to 0FFFFH as shown in Figure 5 (Word Addresses) 1FFFFH 16-Kbyte BOOT BLOCK 1DFFFH 1E000H 8-Kbyte PARAMETER BLOCK 1CFFFH 1D000H 8-Kbyte PARAMETER BLOCK 1BFFFH 1C000H 96-Kbyte MAIN BLOCK 0FFFFH 10000H 128-Kbyte MAIN BLOCK 00000H Figure 5 A28F200BX-T Memory Map 30 PRODUCT FAMILY PRINCIPLES OF OPERATION Flash memory augments EPROM functionality with in-circuit electrical write and erase The 2-Mbit flash family utilizes a Command User Interface (CUI) and internally generated and timed algorithms to simplify write and erase operations The CUI allows for 100% TTL-level control inputs fixed power supplies during erasure and program- ming and maximum EPROM compatibility In the absence of high voltage on the VPP pin the 2-Mbit boot block flash family will only successfully execute the following commands Read Array Read Status Register Clear Status Register and Intelli- gent Identifier mode The device provides standard EPROM read standby and output disable opera- tions Manufacturer Identification and Device Identi- fication data can be accessed through the CUI or through the standard EPROM A9 high voltage ac- cess (VID) for PROM programming equipment The same EPROM read standby and output disable functions are available when high voltage is applied to the VPP pin In addition high voltage on VPP al- lows write and erase of the device All functions as- sociated with altering memory contents write and erase Intelligent Identifier read and Read Status are accessed via the CUI The purpose of the Write State Machine (WSM) is to completely automate the write and erasure of the device The WSM will begin operation upon receipt of a signal from the CUI and will report status back through a Status Register The CUI will handle the WE interface to the data and address latches as well as system software requests for status while the WSM is in operation 31 Bus Operations Flash memory reads erases and writes in-system via the local CPU All bus cycles to or from the flash memory conform to standard microprocessor bus cycles 10 |
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