Other brands and names are the property of their respective owners

Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or

copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make

changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

November 1995

COPYRIGHT

INTEL CORPORATION 1995

Order Number 290500-003

A28F200BX-TB

2-MBIT (128K x 16 256K x 8) BOOT BLOCK

FLASH MEMORY FAMILY

Automotive

Y

x8x16 InputOutput Architecture

A28F200BX-T A28F200BX-B

For High Performance and High

Integration 16-bit and 32-bit CPUs

Y

Optimized High Density Blocked

Architecture

One 16 KB Protected Boot Block

Two 8 KB Parameter Blocks

One 96 KB Main Block

One 128 KB Main Block

Top or Bottom Boot Locations

Y

Extended Cycling Capability

1000 Block Erase Cycles

Y

Automated WordByte Write and

Block Erase

Command User Interface

Status Register

Erase Suspend Capability

Y

SRAM-Compatible Write Interface

Y

Automatic Power Savings Feature

Static Operation

Y

Hardware Data Protection Feature

EraseWrite Lockout during Power

Transitions

Y

Very High-Performance Read

90 ns Maximum Access Time

45 ns Maximum Output Enable Time

Y

Low Power Consumption

25 mA Typical Active Read Current

Y

Deep Power-DownReset Input

Acts as Reset for Boot Operations

Y

Automotive Temperature Operation

b

Y

Write Protection for Boot Block

Y

Industry Standard Surface Mount

Packaging

JEDEC ROM Compatible

44-Lead PSOP

Y

12V WordByte Write and Block Erase

Y

5V Read

Y

Independent Software Vendor Support