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BN87C51FB Datasheet(PDF) 18 Page - Intel Corporation |
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BN87C51FB Datasheet(HTML) 18 Page - Intel Corporation |
18 / 18 page AUTOMOTIVE 87C51FAFBFCFC-20 DATA SHEET REVISION HISTORY The following are key differences between this data sheet and the -002 revision of the data sheet 1 The data sheet has been revised from the 87C51FB87C51FC to the 87C51FA87C51FB87C51FC 87C51FC-20 and includes the 20 MHz 87C51FC 2 RST pin in Figure 3 has been changed to RESET pin 3 Reference to Application Note AP-486 was added on page 5 4 The ICC specification has been corrected in the DC Characteristics section 5 The 20 MHz ICC max values have been added 6 20 MHz 87C51FC timings information were added to the External Program Memory Characteristics table DATA SHEET REVISION HISTORY The following are key differences between this data sheet and the -001 version of the data sheet 1 ‘‘NC’’ pin labels changed to ‘‘Reserved’’ in Figure 3 2 Capacitor value for ceramic resonators deleted in Figure 4 3 Replaced A0 – A15 with P10 – P17 P20 – P25 (EPROM programming and verification waveforms) 4 Replaced D0 – D7 with P0 (EPROM programming and verification waveforms) 5 Combined the 87C51FB and 87C51FC data sheets The following are the key differences between the previous 87C51FB data sheet versions and this new data sheet (rev-001) 1 The data sheet has been revised from a 83C51FB87C51FB to an 87C51FB data sheet only 2 The data sheet has been revised to specify AC and DC parameters to VCC e 5V g20% instead of VCC e 5V g10% 3 The 87C51FB is now offered in a 35 MHz – 20 MHz version 4 The RST description has been modified to clarify the reset operation when the oscillator is not running 5 Figure 4 (Oscillator Connections) has been changed for Ceramic Resonators 6 A description of RFI Reduction Mode has been added 7 VOH1 IIL ITL and ICC DC Characteristics have been revised 8 Note 1 of the DC Characteristics has been clarified 9 The External Clock Drive diagram has been modified to include 16 MHz and 20 MHz device types 10 The Float Waveforms diagram has been revised for greater clarity 11 Table 4 EPROM Programming Modes has been modified included logic levels for P33 and three pro- gram lock bits 12 The Encryption Array section now states that six address lines are used to select a byte from the Encryp- tion Array instead of five 13 The IPP specification in the EPROM Programming and Verification Characteristics has been increased to 75 mA 18 |
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