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S80C186EC20 Datasheet(PDF) 13 Page - Intel Corporation |
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S80C186EC20 Datasheet(HTML) 13 Page - Intel Corporation |
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13 / 57 page  80C186EC188EC 80L186EC188EC Table 2 Pin Descriptions (Continued) Pin Name Pin Input Output Pin Description Type Type States PEREQ I A(L) Processor Extension REQuest signals that a data transfer between an 80C187 Numerics Processor Extension and Memory is pending Systems not using an 80C187 must tie this pin to VSS This signal does not exist on the 80C188EC80L188EC UCS O H(1) Upper Chip Select will go active whenever the address of a memory or IO bus cycle is within the address range R(1) programmed by the user After reset UCS is configured to I(1) be active for memory accesses between 0FFC00H and P(1) 0FFFFFH LCS O H(1) Lower Chip Select will go active whenever the address of a memory or IO bus cycle is within the address range R(1) programmed by the user LCS is inactive after a reset I(1) P(1) P10GCS0 O H(X)H(1) These pins provide a multiplexed function If enabled each pin can provide a General purpose Chip Select P11GCS1 R(1) output which will go active whenever the address of a P12GCS2 I(X)I(1) memory or IO bus cycle is within the address limitations P13GCS3 P(X)P(1) programmed by the user When not programmed as a P14GCS4 Chip-Select each pin may be used as a general purpose P15GCS5 output port P16GCS6 P17GCS7 T0OUT O H(Q) Timer OUTput pins can be programmed to provide single clock or continuous waveform generation depending on T1OUT R(1) the timer mode selected I(Q) P(X) T0IN I A(L) Timer INput is used either as clock or control signals depending on the timer mode selected This pin may be T1IN A(E) either level or edge sensitive depending on the programming mode INT70 I A(L) Maskable INTerrupt input will cause a vector to a specific Type interrupt routine The INT60 pins can be used as A(E) cascade inputs from slave 8259A devices The INT pins can be configured as level or edge sensitive INTA O H(1) INTerrupt Acknowledge output is a handshaking signal used by external 82C59A Programmable Interrupt R(1) Controllers I(1) P(1) P35 IO A(L) H(X) Bidirectional open-drain port pins P34 R(Z) I(X) H(X) P33DMAI1 O H(X) DMA Interrupt output goes active to indicate that the channel has completed a transfer DMAI1 and DMAI0 are P32DMAI0 R(0) multiplexed with output only port functions I(Q) P(X) NOTE Pin names in parentheses apply to the 80C188EC80L188EC 13 |
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