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S80C186EC20 Datasheet(PDF) 53 Page - Intel Corporation |
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S80C186EC20 Datasheet(HTML) 53 Page - Intel Corporation |
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53 / 57 page  80C186EC188EC 80L186EC188EC INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EC 80C188EC Comments Clock Clock Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed) 1111011w mod101 r m Register-Byte 25–28 25–28 Register-Word 34–37 34–37 Memory-Byte 31–34 32–34 Memory-Word 40–43 40–43 IMUL e Integer Immediate multiply 011010s1 mod reg r m data data if se0 22–25 22–25 (signed) 29–32 29–32 DIV e Divide (unsigned) 1111011w mod110 r m Register-Byte 29 29 Register-Word 38 38 Memory-Byte 35 35 Memory-Word 44 44 IDIV e Integer divide (signed) 1111011w mod111 r m Register-Byte 44–52 44–52 Register-Word 53–61 53–61 Memory-Byte 50–58 50–58 Memory-Word 59–67 59–67 AAM e ASCII adjust for multiply 11010100 00001010 19 19 AAD e ASCII adjust for divide 11010101 00001010 15 15 CBW e Convert byte to word 10011000 2 2 CWD e Convert word to double word 10011001 4 4 LOGIC ShiftRotate Instructions RegisterMemory by 1 1101000w mod TTT r m 215 215 RegisterMemory by CL 1101001w mod TTT r m 5an17an5an17an RegisterMemory by Count 1100000w mod TTT r m count 5an17an5an17an TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHLSAL 101 SHR 111 SAR AND e And Regmemory and register to either 001000dw mod reg r m 310 310 Immediate to registermemory 1000000w mod100 r m data data if we1 416 416 Immediate to accumulator 0010010w data data if we1 34 34 816-bit TESTeAnd function to flags no result Registermemory and register 1000010w mod reg r m 310 310 Immediate data and registermemory 1111011w mod000 r m data data if we1 410 410 Immediate data and accumulator 1010100w data data if we1 34 34 816-bit OReOr Regmemory and register to either 000010dw mod reg r m 310 310 Immediate to registermemory 1000000w mod001 r m data data if we1 416 416 Immediate to accumulator 0000110w data data if we1 34 34 816-bit Shaded areas indicate instructions not available in 80868088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers 53 |
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