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S80C186EC20 Datasheet(PDF) 50 Page - Intel Corporation |
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S80C186EC20 Datasheet(HTML) 50 Page - Intel Corporation |
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50 / 57 page  80C186EC188EC 80L186EC188EC 80C186EC80C188EC EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions The fol- lowing instruction timings represent the minimum execution time in clock cycles for each instruction The timings given are based on the following as- sumptions The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states or bus HOLDs occur All word-data is located on even-address bound- aries (80C186EC only) All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address All instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (BIU) and exe- cution unit With a 16-bit BIU the 80C186EC has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time Therefore actual program execu- tion time will not be substantially greater than that derived from adding the instruction timings shown The 80C188EC 8-bit BIU is limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time Therefore actual program execution time will be substantially greater than that derived from adding the instruction timings shown 50 |
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