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S80C186EC20 Datasheet(PDF) 5 Page - Intel Corporation |
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S80C186EC20 Datasheet(HTML) 5 Page - Intel Corporation |
5 / 57 page 80C186EC188EC 80L186EC188EC 272434 – 2 NOTE 1 The LC network is only required when using a third overtone crystal Figure 2 80C186EC Clock Connections 80C186EC PERIPHERAL ARCHITECTURE The 80C186EC integrates several common system peripherals with a CPU core to create a compact yet powerful system The integrated peripherals are de- signed to be flexbile and provide logical interconnec- tions between supporting units (eg the DMA unit can accept requests from the Serial Communica- tions Unit) The list of integrated peripherals includes Two cascaded 8259A compatible Programma- ble Interrupt Controllers 3-Channel TimerCounter Unit 2-Channel Serial Communications Unit 4-Channel DMA Unit 10-Output Chip-Select Unit 32-bit Watchdog Timer Unit IO Port Unit Refresh Control Unit Power Management Unit The registers associated with each integrated pe- ripheral are contained within a 128 x 16-bit register file called the Peripheral Control Block (PCB) The base address of the PCB is programmable and can be located on any 256 byte address boundary in ei- ther memory or IO space Figure 3 provides a list of the registers associated with the PCB The Register Bit Summary individually lists all of the registers and identifies each of their programming attributes 5 |
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