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S80C186EC20 Datasheet(PDF) 35 Page - Intel Corporation |
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S80C186EC20 Datasheet(HTML) 35 Page - Intel Corporation |
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35 / 57 page  80C186EC188EC 80L186EC188EC AC Characteristics80L186EC16 (Continued) NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 14 for capacitive derating information 5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF 6 See Figure 15 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A1916 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation Relative Timings (80C186EC-252013 80L186EC-1613) Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS TLHLL ALE Active Pulse Width T b 15 ns TAVLL AD Valid Setup before ALE Falls T b 10 ns TPLLL Chip Select Valid before ALE Falls T b 10 ns 1 TLLAX AD Hold after ALE Falls T b 10 ns TLLWL ALE Falling to WR Falling T b 15 ns 1 TLLRL ALE Falling to RD Falling T b 15 ns 1 TWHLH WR Rising to Next ALE Rising T b 10 ns 1 TAFRL AD Float to RD Falling 0 ns TRLRH RD Active Pulse Width 2T b 5ns 2 TWLWH WR Active Pulse Width 2T b 5ns 2 TRHAX RD Rising to Next Address Active T b 15 ns TWHDX Output Data Hold after WR Rising T b 15 ns TWHPH WR Rise to Chip Select Rise T b 10 ns 1 TRHPH RD Rise to Chip Select Rise T b 10 ns 1 TPHPL Chip Select Inactive to Next Chip T b 10 ns 1 Select Active TOVRH ONCE Active Setup to RESIN Rising T ns TRHOX ONCE Hold after RESIN Rise T ns TIHIL INTA High to Next INTA Low 4T b 5ns 4 during INTA Cycle TILIH INTA Active Pulse Width 2T b 5ns 2 4 TCVIL CAS20 Setup before 2nd INTA 8T ns 2 4 Pulse Low TILCX CAS20 Hold after 2nd INTA Pulse Low 4T ns 2 4 TIRES Interrupt Resolution Time 150 ns 3 TIRLH IR Low Time to Reset Edge Detector 50 ns TIRHIF IR Hold Time after 1st INTA Falling 25 ns 4 5 35 |
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