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S80L188EC16 Datasheet(PDF) 4 Page - Intel Corporation |
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S80L188EC16 Datasheet(HTML) 4 Page - Intel Corporation |
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4 / 57 page  80C186EC188EC 80L186EC188EC INTRODUCTION Unless specifically noted all references to the 80C186EC apply to the 80C188EC 80L186EC and 80L188EC References to pins that differ between the 80C186EC80L186EC and the 80C188EC 80L188EC are given in parentheses The ‘‘L’’ in the part number denotes low voltage operation Physi- cally and functionally the ‘‘C’’ and ‘‘L’’ devices are identical The 80C186EC is one of the highest integration members of the 186 Integrated Processor Family Two serial ports are provided for services such as interprocessor communication diagnostics and mo- dem interfacing Four DMA channels allow for high speed data movement as well as support of the on- board serial ports A flexible chip select unit simpli- fies memory and peripheral interfacing The three general purpose timercounters can be used for a variety of time measurement and waveform genera- tion tasks A watchdog timer is provided to insure system integrity even in the most hostile of environ- ments Two 8259A compatible interrupt controllers handle internal interrupts and up to 57 external in- terrupt requests A DRAM refresh unit and 24 multi- plexed IO ports round out the feature set of the 80C186EC The future set of the 80C186EC meets the needs of low-power space-critical applications Low-power applications benefit from the static design of the CPU and the integrated peripherals as well as low voltage operation Minimum current consumption is achieved by providing a powerdown mode that halts operaton of the device and freezes the clock cir- cuits Peripheral design enhancements ensure that non-initialized peripherals consume little current The 80L186EC is the 3V version of the 80C186EC The 80L186EC is functionally identical to the 80C186EC embedded processor Current 80C186EC users can easily upgrade their designs to use the 80L186EC and benefit from the reduced power consumption inherent in 3V operation Figure 1 shows a block diagram of the 80C186EC 80C188EC The execution unit (EU) is an enhanced 8086 CPU core that includes dedicated hardware to speed up effective address calculations enhanced execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions string move instructions that operate at full bus bandwidth ten new instructions and fully static oper- ation The bus interface unit (BIU) is the same as that found on the original 186 family products ex- cept the queue-status mode has been deleted and buffer interface control has been changed to ease system design timings An independent internal bus is used for communication between the BIU and on- chip peripherals 80C186EC CORE ARCHITECTURE Bus Interface Unit The 80C186EC core incorporates a bus controller that generates local bus control signals In addition it employs a HOLDHLDA protocol to share the local bus with other bus masters The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data (for write operations) in- formation It is also responsible for reading data from the local bus during a read operation A ready input pin is provided to extend a bus cycle beyond the minimum four states (clocks) The bus controller also generates two control sig- nals (DEN and DTR) when interfacing to external transceiver chips This capability allows the addition of transceivers for simple buffering of the multi- plexed addressdata bus Clock Generator The 80C186EC provides an on-chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divide- by-two counter and three low-power operating modes The oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network Alternatively the oscilla- tor circuit may be driven from an external clock source Figure 2 shows the various operating modes of the oscillator circuit The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter This counter is used to drive all internal phase clocks and the exter- nal CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- tem components All AC timings are referenced to CLKOUT The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Res) 40X max C0 (Shunt Capacitance of Crystal) 70 pF max CL (Load Capacitance) 20 pF g2pF Drive Level 1 mW (max) 4 |
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