 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
S80L188EC16 Datasheet(PDF) 12 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
S80L188EC16 Datasheet(HTML) 12 Page - Intel Corporation |
|
|
12 / 57 page  80C186EC188EC 80L186EC188EC Table 2 Pin Descriptions (Continued) Pin Name Pin Input Output Pin Description Type Type States RD O H(Z) ReaD output signals that the accessed memory or IO device should drive data information onto the data bus R(Z) I(1) P(1) WR O H(Z) WRite output signals that data available on the data bus are to be written into the accessed memory or IO device R(Z) I(1) P(1) READY I A(L) READY input to signal the completion of a bus cycle READY must be active to terminate any 80C186EC bus cycle unless S(L) it is ignored by correctly programming the Chip-Select unit (Note 1) DEN O H(Z) Data ENable output to control the enable of bi-directional transceivers in a buffered system DEN is active only when R(Z) data is to be transferred on the bus I(1) P(1) DTR O H(Z) Data TransmitReceive output controls the direction of a bi- directional buffer in a buffered system R(Z) I(X) P(X) LOCK IO A(L) H(Z) LOCK output indicates that the bus cycle in progress is not interruptable The processor will not service other bus R(Z) requests (such as HOLD) while LOCK is active This pin is I(X) configured as a weakly held high input while RESIN is active P(X) and must not be driven low HOLD I A(L) HOLD request input to signal that an external bus master wishes to gain control of the local bus The processor will relinquish control of the local bus between instruction boundaries that are not LOCKed HLDA O H(1) HoLD Acknowledge output to indicate that the processor has relinquished control of the local bus When HLDA is R(0) asserted the processor will (or has) floated its data bus and I(0) control signals allowing another bus master to drive the P(0) signals directly NCS O H(1) Numerics Coprocessor Select output is generated when acessing a numerics coprocessor This signal does not exist R(1) on the 80C188EC80L188EC I(1) P(1) ERROR I A(L) ERROR input that indicates the last numerics processor extension operation resulted in an exception condition An interrupt TYPE 16 is generated if ERROR is sampled active at the beginning of a numerics operation Systems not using an 80C187 must tie ERROR to VCC This signal does not exist on the 80C188EC80L188EC NOTE Pin names in parentheses apply to the 80C188EC80L188EC 12 |
Similar Part No. - S80L188EC16 |
|
Similar Description - S80L188EC16 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
