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82093AA Datasheet(PDF) 1 Page - Intel Corporation |
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82093AA Datasheet(HTML) 1 Page - Intel Corporation |
1 / 20 page PRELIMINARY Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The 82093AA IOAPIC may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property of their respective owners. © INTEL CORPORATION 1996 May 1996 Order Number: 290566-001 Provides Multiprocessor Interrupt Management Dynamic Interrupt Distribution- Routing Interrupt to the Lowest Priority Processor Software Programmable Control of Interrupt Inputs Off Loads Interrupt Related Traffic From the Memory Bus 24 Programmable Interrupts 13 ISA Interrupts Supported 4 PCI Interrupts 1 Interrupt/SMI# Rerouting 2 Motherboard Interrupts 1 Interrupt Used for INTR Input 3 General Purpose Interrupts Independently Programmable for Edge/Level Sensitivity Interrupts Each Interrupt Can Be Programmed to Respond to Active High or Low Inputs X-Bus Interface CS For Flexible Decode of the IOAPIC Device. Index Register Interface for Optimum Memory Usage Registers are 32-Bit Wide to Match the PCI to Host Bridge Architecture Package 64-Pin PQFP The 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts. Each interrupt pin is individually programmable as either edge or level triggered. The interrupt vector and interrupt steering information can be specified per interrupt. An indirect register accessing scheme optimizes the memory space needed to access the IOAPIC’s internal registers. To increase system flexibility when assigning memory space usage, the The IOAPIC’s 2-register memory space is re-locatable. System Bus Interface APIC Bus Interface Clock And Reset D[7:0] D/I# A[1:0] RD# WR# CS# APCIREQ# APICACK1# APICACK2# RESET CLK APCID[1:0] APCICLK APCID[1:0] APCICLK APCICLK Interrupt Controller Test TESTIN# IOA_BLK Figure 1. IOAPIC Simplified Block Diagram 82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC) |
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