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AD1896 Datasheet(PDF) 25 Page - Analog Devices |
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AD1896 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 28 page  REV. A AD1896 –25– Matched-Phase Mode The matched-phase mode is the mode discussed in the Theory of Operation section that eliminates the phase mismatch between multiple AD1896s. The master AD1896 device transmits its fS_OUT/fS_IN ratio through the SDATA_O pin to the slave AD1896’s TDM_IN pins. The slave AD1896s receive the transmitted fS_OUT/fS_IN ratio and use the transmitted fS_OUT/ fS_IN ratio instead of their own internally derived fS_OUT/fS_IN ratio. The master device can have both its serial ports in slave mode as depicted or either one in master mode. The slave AD1896s must have their MMODE_2, MMODE_1, and MMODE_0 pins set to 100, respectively. LRCLK_I and LRCLK_O may be asynchronous with respect to each other in this mode. Another requirement of the matched-phase mode is that there must be 32 SCLK_O cycles per subframe. The AD1896 will support the matched-phase mode for all serial output data formats, left justified, I 2S, right justified, and TDM. In the case of TDM, the AD1896 shown in the TDM mode operation figure with its TDM_IN tied to ground would be configured as the master, while the rest of the AD1896s in the chain would be configured as slaves with their MMODE_2, MMODE_1, and MMODE_0 pins set to 100, respectively. Please note that in the left-justified, I 2S, and TDM modes, the lower eight bits of each channel subframe are used to transmit the matched-phase data. In right-justified mode, the upper eight bits are used to transmit the matched-phase data. This is shown in Figures 14a and 14b. Bypass Mode When the BYPASS pin is asserted high, the input data bypasses the sample rate converter and is sent directly to the serial output port. Dithering of the output data when the word length is set to less than 24 bits is disabled. This mode is ideal when the input and output sample rates are the same and LRCLK_I and LRCLK_O are synchronous with respect to each other. This mode can also be used for passing through non-AUDIO data since no processing is performed on the input data in this mode. AUDIO DATA LEFT CHANNEL, 24 BITS MATCHED-PHASE DATA, 8 BITS AUDIO DATA RIGHT CHANNEL, 24 BITS MATCHED-PHASE DATA, 8 BITS Figure 14a. Matched-Phase Data Transmission (Left-Justified, I2S, and TDM Mode) AUDIO DATA LEFT CHANNEL, 16 BITS – 24 BITS AUDIO DATA RIGHT CHANNEL, 16 BITS – 24 BITS MATCHED-PHASE DATA, 8 BITS MATCHED-PHASE DATA, 8 BITS Figure 14b. Matched-Phase Data Transmission (Right-Justified Mode) |
Similar Part No. - AD1896_15 |
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Similar Description - AD1896_15 |
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