 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD1896 Datasheet(PDF) 24 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD1896 Datasheet(HTML) 24 Page - Analog Devices |
|
|
24 / 28 page  REV. A AD1896 –24– Serial Data Port Master Clock Modes Either of the AD1896 serial ports can be configured as a master serial data port. However, only one serial port can be a master while the other has to be a slave. In master mode, the AD1896 requires a 256 ¥ fS, 512 ¥ fS, or 768 ¥ fS master clock (MCLK_I). For a maximum master clock frequency of 30 MHz, the maxi- mum sample rate is limited to 96 kHz. In slave mode, sample rates up to 192 kHz can be handled. When either of the serial ports is operated in master mode, the master clock is divided down to derive the associated left/ right subframe clock (LRCLK) and serial bit clock (SCLK). The master clock frequency can be selected for 256, 512, or 768 times the input or output sample rate. Both the input and out- put serial ports will support master mode LRCLK and SCLK generation for all serial modes, left justified, I 2S, right justified, and TDM for the output serial port. Table IV. Serial Data Port Clock Modes MMODE_0/ MMODE_1/ MMODE_2 Interface Format 210 000Both serial ports are in slave mode. 001 Output serial port is master with 768 ¥ fS_OUT. 010Output serial port is master with 512 ¥ fS_OUT. 011 Output serial port is master with 256 ¥ fS_OUT. 100Matched-phase Mode 101 Input serial port is master with 768 ¥ fS_IN. 110 Input serial port is master with 512 ¥ fS_IN. 111 Input serial port is master with 256 ¥ fS_IN. AD1896 TDM_IN SDATA_O LRCLK_O CLOCK-MASTER AND PHASE-MASTER M1 M2 M0 1 0 1 SCLK_O SHARC DSP DR0 RFS0 RCLK0 SLAVE-1 SLAVE-n STANDARD MODE MATCHED-PHASE MODE AD1896 TDM_IN SDATA_O LRCLK_O M1 M2 M0 0 0 0 0 1 0 SCLK_O AD1896 TDM_IN SDATA_O LRCLK_O M1 M2 M0 SCLK_O 0 0 0 0 1 0 Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1896 Being Clock-Master) MATCHED-PHASE MODE (NON-TDM MODE) APPLICATION AD1896 SLAVE1 M2 M1 M0 AD1896 TDM_IN SDATA_I LRCLK_I SCLK_I MCLK RESET SDATA_O LRCLK_O SCLK_O PHASE-MASTER M2 M1 M0 AD1896 SLAVE2 M2 M1 M0 AD1896 SLAVEn M2 M1 M0 0 0 0 1 0 0 1 0 0 1 0 0 LRCLKI (fS_IN) SCLKI LRCLKO (fS_OUT) SCLKO (64fS_OUT) MCLK RESET SDOm SDO1 SDO2 SDOn TDM_IN SDATA_I LRCLK_I SCLK_I MCLK RESET SDATA_O LRCLK_O SCLK_O TDM_IN SDATA_I LRCLK_I SCLK_I MCLK RESET SDATA_O LRCLK_O SCLK_O TDM_IN SDATA_I LRCLK_I SCLK_I MCLK RESET SDATA_O LRCLK_O SCLK_O Figure 13. Typical Configuration for Matched-Phase Mode Operation |
Similar Part No. - AD1896_15 |
|
Similar Description - AD1896_15 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
