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AD1896 Datasheet(PDF) 21 Page - Analog Devices |
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AD1896 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 28 page  REV. A AD1896 –21– However, the hysteresis of the fS_OUT/fS_IN ratio circuit can cause phase mismatching between two AD1896s operating with the same input clock and the same output clock. Since the hyster- esis requires a difference of more than two fS_OUT periods for the fS_OUT/fS_IN ratio to be updated, two AD1896s may have dif- ferences in their ratios from 0 to 4 fS_OUT period counts. The fS_OUT/fS_IN ratio adjusts the filter length of the AD1896, which corresponds directly with the group delay. Thus, the magnitude in the phase difference will depend upon the resolution of the fS_OUT and fS_IN counters. The greater the resolution of the counters, the smaller the phase difference error will be. The fS_IN and fS_OUT counters of the AD1896 have three bits of extra resolution over the AD1890, which reduces the phase mismatch error by a factor of 8. However, an additional feature was added to the AD1896 to eliminate the phase mismatching completely. One AD1896 can set the fS_OUT/fS_IN ratio of other AD1896s by transmitting its fS_OUT/fS_IN ratio through the serial output port. OPERATING FEATURES RESET and Power-Down When RESET is asserted low, the AD1896 will turn off the master clock input to the AD1896, MCLK_I, initialize all of its internal registers to their default values, and three-state all of the I/O pins. While RESET is active low, the AD1896 is consuming minimum power. For the lowest possible power consumption while RESET is active low, all of the input pins to the AD1896 should be static. When RESET is deasserted, the AD1896 begins its initialization routine where all locations in the FIFO are initialized to zero, MUTE_OUT is asserted high, and any I/O pins configured as outputs are enabled. When RESET is deasserted, the master serial port clock pins SCLK_I/O and LRCLK_I/O become active after 1024 MCLK-I cycles. The mute control counter, which controls the soft mute attenuation of the input samples, is initialized to maximum attenuation, –144 dB (see the Mute Control section). When asserting RESET and deasserting RESET, the RESET should be held low for a minimum of five MCLK_I cycles. During power-up, the RESET should be held low until the power supplies have stabilized. It is recommended that the AD1896 be reset when changing modes. Power Supply and Voltage Reference The AD1896 is designed for 3 V operation with 5 V input toler- ance on the input pins. VDD_CORE is the 3 V supply that is used to power the core logic of the AD1896 and to drive the output pins. VDD_IO is used to set the input voltage tolerance of the input pins. In order for the input pins to be 5 V input tolerant, VDD_IO must be connected to a 5 V supply. If the input pins do not have to be 5 V input tolerant, then VDD_IO can be connected to VDD_CORE. VDD_IO should never be less than VDD_CORE. VDD_CORE and VDD_IO should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize power supply and ground bounce caused by inductance in the traces. A bulk alu- minium electrolytic capacitor of 47 mF should also be provided on the same PC board as the AD1896. Digital Filter Group Delay The group delay of the digital filter may be selected by the logic pin GRPDLYS. As mentioned in the Theory of Operation section, this pin is particularly useful in varispeed applications. The GRPDLYS pin has an internal pull-up resistor of approximately 33 k W to VDD_CORE. When GRPDLYS is high, the filter group delay will be short and is given by the equation: GDS ff for f f GDS ff f f for f f S_IN S_IN S_OUT S_IN S_IN S_IN S_IN S_OUT S_OUT S_IN =+ > =+ Ê ËÁ ˆ ¯˜ ¥ Ê ËÁ ˆ ¯˜ < 16 32 16 32 seconds seconds For short filter group delay, the GRPDLYS pin can be left open. When GRPDLYS is low, the group delay of the filter will be long and is given by the equation: GDL ff for f f GDL ff f f for f f S_IN S_IN S_OUT S_IN S_IN S_IN S_IN S_OUT S_OUT S_IN =+ > =+ Ê ËÁ ˆ ¯˜ ¥ Ê ËÁ ˆ ¯˜ < 64 32 64 32 seconds seconds NOTE: For the long group delay mode, the decimation ratio is limited to less than 7:1. Mute Control When the MUTE_IN pin is asserted high, the MUTE_IN control will perform a soft mute by linearly decreasing the input data to the AD1896 FIFO to zero, –144 dB attenuation. When MUTE_IN is deasserted low, the MUTE_IN control will linearly decrease the attenuation of the input data to 0 dB. A 12-bit counter, clocked by LRCLK_I, is used to control the mute attenuation. Therefore, the time it will take from the assertion of MUTE_IN to –144 dB full mute attenuation is 4096/LRCLK_I seconds. Likewise, the time it will take to reach 0 dB mute attenuation from the deassertion of MUTE_IN is 4096/LRCLK_I seconds. Upon RESET, or a change in the sample rate between LRCLK_I and LRCLK_O, the MUTE_OUT pin will be asserted high. The MUTE_OUT pin will remain asserted high until the digital servo loop’s internal fast settling mode has completed. When the digital servo loop has switched to slow settling mode, the MUTE_OUT pin will deassert. While MUTE_OUT is asserted, the MUTE_IN pin should be asserted as well to prevent any major distortion in the audio output samples. Master Clock A digital clock connected to the MCLK_I pin or a fundamental or third overtone crystal connected between MCLK_I and MCLK_O can be used to generate the master clock, MCLK_I. The MCLK_I pin can be 5 V input tolerant just like any of the other AD1896 input pins. A fundamental mode crystal can be inserted between MCLK_I and MCLK_O for master clock frequency generation up to 27 MHz. For master clock fre- quency generation with a crystal beyond 27 MHz, it is recommended that the user use a third overtone crystal and to add an LC filter at the output of MCLK_O to filter out the fundamental, do not notch filter the fundamental. Please refer to your quartz crystal supplier for values for external capaci- tors and inductor components. |
Similar Part No. - AD1896_15 |
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Similar Description - AD1896_15 |
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