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AD1896 Datasheet(PDF) 17 Page - Analog Devices |
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AD1896 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 28 page  REV. A AD1896 –17– (Continued from Page 1) The digital servo loop measures the time difference between the input and output sample rates within 5 ps. This is necessary in order to select the correct polyphase filter coefficient. The digital servo loop has excellent jitter rejection for both input and output sample rates as well as the master clock. The jitter rejec- tion begins at less than 1 Hz. This requires a long settling time whenever RESET is deasserted or when the input or output sample rate changes. To reduce the settling time, upon deassertion of RESET or a change in a sample rate, the digital servo loop enters the fast settling mode. When the digital servo loop has adequately settled in the fast mode, it switches into the normal or slow settling mode and continues to settle until the time difference measurement between input and output sample rates is within 5 ps. During fast mode, the MUTE_OUT signal is asserted high. Normally, the MUTE_OUT is connected to the MUTE_IN pin. The MUTE_IN signal is used to softly mute the AD1896 upon assertion and softly unmute the AD1896 when it is deasserted. The sample rate ratio circuit is used to scale the filter length of the FIR filter for decimation. Hysteresis in measuring the sample rate ratio is used to avoid oscillations in the scaling of the filter length, which would cause distortion on the output. However, when multiple AD1896s are used with the same serial input port clock and the same serial output port clock, the hys- teresis causes different group delays between multiple AD1896s. A phase-matching mode feature was added to the AD1896 to address this problem. In phase-matching mode, one AD1896, the master, transmits its sample rate ratio to the other AD1896s, the slaves, so that the group delay between the multiple AD1896s remains the same. The group delay of the AD1896 can be adjusted for short or long delay. An address offset is added to the write pointer of the FIFO in the sample rate converter. This offset is set to 16 for short delay and 64 for long delay. In long delay, the group delay is effectively increased by 48 input sample clocks. The sample rate converter of the AD1896 can be bypassed altogether using the bypass mode. In bypass mode, the AD1896’s serial input data is directly passed to the serial output port with- out any dithering. This is useful for passing through nonaudio data or when the input and output sample rates are synchronous to one another and the sample rate ratio is exactly 1 to 1. The AD1896 is a 3.3 V, 5 V input tolerant part and is available in a 28-lead SSOP package. The AD1896 is 5 V input-tolerant only when the VDD_IO supply pin is supplied with 5 V. |
Similar Part No. - AD1896_15 |
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Similar Description - AD1896_15 |
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