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AD1895 Datasheet(PDF) 17 Page - Analog Devices |
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AD1895 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 24 page  REV. B AD1895 –17– FREQUENCY DOMAIN OF SAMPLES AT fS_IN FREQUENCY DOMAIN OF THE INTERPOLATION FREQUENCY DOMAIN OF fS_OUT RESAMPLING FREQUENCY DOMAIN AFTER RESAMPLING IN OUT fS_IN fS_OUT INTERPOLATE BY N LOW-PASS FILTER ZERO-ORDER HOLD fS_IN 220 fS_IN 220 fS_IN 220 fS_IN SIN(X)/X OF ZERO-ORDER HOLD Figure 6. Frequency Domain of the Interpolation and Resampling HARDWARE MODEL The output rate of the low-pass filter of Figure 5 would be the interpolation rate, 2 20 × 192000 kHz = 201.3 GHz. Sampling at a rate of 201.3 GHz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. However, since interpolation by 2 20 involves zero-stuffing 220–1 samples between each fS_IN sample, most of the multiplies in the low-pass FIR filter are by zero. A further reduction can be realized by the fact that since only one interpolated sample is taken at the output at the fS_OUT rate, only one convolution needs to be performed per fS_OUT period instead of 2 20 convo- lutions. A 64-tap FIR filter for each fS_OUT sample is sufficient to suppress the images caused by the interpolation. The difficulty with the above approach is that the correct inter- polated sample needs to be selected upon the arrival of fS_OUT. Since there are 2 20 possible convolutions per f S_OUT period, the arrival of the fS_OUT clock must be measured with an accuracy of 1/201.3 GHz = 4.96 ps. Measuring the fS_OUT period with a clock of 201.3 GHz frequency is clearly impossible; instead, several coarse measurements of the fS_OUT clock period are made and averaged over time. Another difficulty with the above approach is the number of coefficients required. Since there are 2 20 possible convolutions with a 64-tap FIR filter, there needs to be 2 20 polyphase coeffi- cients for each tap, which requires a total of 2 26 coefficients. To reduce the number of coefficients in ROM, the AD1895 stores a small subset of coefficients and performs a high order interpola- tion between the stored coefficients. So far, the above approach works for the case of fS_OUT > fS_IN. However, in the case when the output sample rate, fS_OUT, is less than the input sample rate, fS_IN, the ROM starting address, input data, and length of the convolution must be scaled. As the input sample rate rises over the output sample rate, the antialiasing filter’s cutoff fre- quency has to be lowered because the Nyquist frequency of the output samples is less than the Nyquist frequency of the input samples. To move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of fS_IN/fS_OUT. This tech- nique is supported by the Fourier transform property that if f(t) is F( ω), then f(k × t) is F(ω/k). Thus, the range of decimation is simply limited by the size of the RAM. THE SAMPLE RATE CONVERTER ARCHITECTURE The architecture of the sample rate converter is shown in Figure 7. The sample rate converter’s FIFO block adjusts the left and right input samples and stores them for the FIR filter’s convolution cycle. The fS_IN counter provides the write address to the FIFO block and the ramp input to the digital servo loop. The ROM stores the coefficients for the FIR filter convolution and performs a high order interpolation between the stored coefficients. The sample rate ratio block measures the sample rate for dynami- cally altering the ROM coefficients and scaling of the FIR filter length as well as the input data. The digital servo loop automatically tracks the fS_IN and fS_OUT sample rates and provides the RAM and ROM start addresses for the start of the FIR filter convolution. RIGHT DATA IN LEFT DATA IN FIFO ROM A ROM B ROM C ROM D HIGH ORDER INTERP DIGITAL SERVO LOOP FIR FILTER SAMPLE RATE RATIO f S_IN COUNTER SAMPLE RATE RATIO EXTERNAL RATIO fS_IN fS_OUT L/R DATA OUT Figure 7. Architecture of the Sample Rate Converter The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM. The input data is scaled by the sample rate ratio because as the FIR filter length of the convolution increases, so does the amplitude of the convo- lution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by fS_OUT/fS_IN when fS_OUT < fS_IN. The FIFO also scales the input data for muting and unmuting the AD1895. The RAM in the FIFO is 512 words deep for both left and right channels. A small offset of 16 is added to the write address provided by the fS_IN counter to prevent the RAM read pointer from ever overlapping the write address. The maximum deci- mation rate can be calculated from the RAM word depth as (512 – 16)/64 taps = 7.75 and a small offset. |
Similar Part No. - AD1895_15 |
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Similar Description - AD1895_15 |
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