COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

10



Figure 8. Full Flag Timing

Figure 9. Empty Flag Timing

NOTE:

1.

The Latency Timings apply only at the Empty Boundary (

EF = LOW).

NOTE:

1. Only one of the two write enable inputs,

WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

NEXT DATA READ

DATA READ

WCLK

FF

WEN1

WEN2

(If Applicable)

RCLK

REN1,

REN2

DATA IN OUTPUT REGISTER

OE LOW

NO WRITE

NO WRITE

2655 drw 10

(1)

(1)

NO WRITE

DATA WRITE 1

DATA WRITE 2

WCLK

RCLK

EF

REN1,

REN2

OE

DATA READ

(1)

DATA IN OUTPUT REGISTER

(1)

LOW

WEN2

(If Applicable)

WEN1

2655 drw 11