9



COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

(1)

WCLK

WEN2

(If Applicable)

RCLK

EF

REN1,

REN2

OE

WEN1

2655 drw 09

NOTE:

EF to change during the current clock cycle. If the time between the rising edge of RCLK

EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

NOTE:

1.

The Latency Timings apply only at the Empty Boundary (

EF = LOW).

Figure 7. First Data Word Latency Timing

NO OPERATION

VALID DATA

(1)

RCLK

REN1,

REN2

EF

OE

WCLK

WEN1

WEN2

2655 drw 08