5.14

14

IDT72251 CMOS SyncFIFO

™

8192 x 9

COMMERCIAL TEMPERATURE RANGES

WCLK

WEN1

WEN2

PAE

RCLK

REN1,

REN2

(If Applicable)

(3)

(1)

n words in FIFO

n+1 words in FIFO

2655 drw 13

NOTES:

1. PAE offset = n.

PAE to change during that clock cycle. If the time between the rising

PAE may not change state until the next RCLK rising edge.

3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when

PAE goes LOW.

Figure 11. Programmable Empty Flag Timing